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1. 发明授权

US07674682B2 Capacitor integration at top-metal level with a protective cladding for copper surface protection 有权
标题翻译：电容器集成在顶级金属层与铜表面保护用保护层
公开(公告)号：US07674682B2
公开(公告)日：2010-03-09
申请号：US10697138
申请日：2003-10-30
申请人： Edmund Burke , Satyavolu S. Papa Rao , Timothy A. Rost
发明人： Edmund Burke , Satyavolu S. Papa Rao , Timothy A. Rost
IPC分类号： H01L21/331
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection cladding (109) for the copper metal (104b) of the top metal interconnect.
摘要翻译：片上去耦电容器（106）及其制造方法。去耦电容器（106）集成在顶部金属互连级（104）处，并且包括用于顶部金属互连的铜金属（104b）的表面保护包层（109）。

2. 发明授权

US06924208B2 Dual mask capacitor for integrated circuits 有权
标题翻译：用于集成电路的双屏蔽电容器
公开(公告)号：US06924208B2
公开(公告)日：2005-08-02
申请号：US10831471
申请日：2004-04-23
申请人： Timothy A. Rost , Edmund Burke , Satyavolu S. Papa Rao , Rose Alyssa Keagy
发明人： Timothy A. Rost , Edmund Burke , Satyavolu S. Papa Rao , Rose Alyssa Keagy
IPC分类号： H01L21/02 , H01L21/768 , H01L21/20
CPC分类号： H01L28/40 , H01L21/76895
摘要： An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.
摘要翻译：本发明的一个实施例是一种电容器，其包括耦合到顶部金属电平10的第一互连层30a的底部电极70，耦合到顶部金属层10的第二互连层30b的电容器电介质90，侧壁105和顶部电极110 本发明的另一个实施例是使用第一掩模140制造电容器以形成材料堆叠的方法，该材料堆叠包括耦合到顶部金属电平10的第一互连层30a的底部电极70，电容器电介质90 和部分顶部电极100.该方法还包括使用第二掩模150以形成耦合到顶部金属层10的第二互连层30b的完整顶部电极。

3. 发明授权

US07015093B2 Capacitor integration at top-metal level with a protection layer for the copper surface 有权
标题翻译：电容器集成在顶级金属层与铜表面的保护层
公开(公告)号：US07015093B2
公开(公告)日：2006-03-21
申请号：US10697139
申请日：2003-10-30
申请人： Satyavolu S. Papa Rao , Timothy A. Rost , Edmund Burke
发明人： Satyavolu S. Papa Rao , Timothy A. Rost , Edmund Burke
IPC分类号： H01L21/8242
CPC分类号： H01L23/5223 , H01L28/65 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection layer (109) for the copper metal (104b) of the top metal interconnect.
摘要翻译：片上去耦电容器（106）及其制造方法。去耦电容器（106）集成在顶部金属互连级（104）处，并且包括用于顶部金属互连的铜金属（104b）的表面保护层（109）。

4. 发明授权

US06898068B2 Dual mask capacitor for integrated circuits 有权
标题翻译：用于集成电路的双屏蔽电容器
公开(公告)号：US06898068B2
公开(公告)日：2005-05-24
申请号：US10669847
申请日：2003-09-24
申请人： Timothy A. Rost , Edmund Burke , Satyavolu S. Papa Rao , Rose Alyssa Keagy
发明人： Timothy A. Rost , Edmund Burke , Satyavolu S. Papa Rao , Rose Alyssa Keagy
IPC分类号： H01L21/02 , H01L21/768 , H01G4/35
CPC分类号： H01L28/40 , H01L21/76895
摘要： An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrodes 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.
摘要翻译：本发明的一个实施例是一种电容器，其包括耦合到顶部金属电平10的第一互连层30a的底部电极70，耦合到顶部金属层10的第二互连层30b的电容器电介质90，侧壁105和顶部电极110 金属等级10。本发明的另一实施例是使用第一掩模140来形成电容器的方法，以形成材料堆叠，该材料堆叠包括耦合到顶部金属电平10的第一互连层30a的底部电极70，电容器电介质90和部分顶部电极100。该方法还包括使用第二掩模150来形成与顶部金属级10的第二互连件30b连接的完整顶部电极。

5. 发明授权

US07291897B2 One mask high density capacitor for integrated circuits 有权
标题翻译：一种用于集成电路的掩模高密度电容器
公开(公告)号：US07291897B2
公开(公告)日：2007-11-06
申请号：US10696816
申请日：2003-10-30
申请人： Timothy A. Rost , Edmund Burke , Satyavolu S. Papa Rao
发明人： Timothy A. Rost , Edmund Burke , Satyavolu S. Papa Rao
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides electrical connection to the top electrode (112) of the decoupling capacitor (106).
摘要翻译：片上去耦电容器（106）及其制造方法。去耦电容器（104）集成在顶部金属互连级（104）处，并且可以仅用一个附加掩模层来实现。去耦电容器（106）形成在铜互连线（104a）上。铝盖层（118）提供与去耦电容器（106）的顶部电极（112）的电连接。

6. 发明授权

US09284656B2 Use of metal phosphorus in metallization of photovoltaic devices and method of fabricating same 有权
标题翻译：在金属化光伏器件中使用金属磷及其制造方法
公开(公告)号：US09284656B2
公开(公告)日：2016-03-15
申请号：US13154058
申请日：2011-06-06
申请人： Kathryn C. Fisher , Qiang Huang , Satyavolu S. Papa Rao
发明人： Kathryn C. Fisher , Qiang Huang , Satyavolu S. Papa Rao
IPC分类号： C25D3/56 , C25D3/58 , H01L21/288 , H01L23/532 , H01L21/768 , H01L31/0224 , C25D3/38 , C25D3/60 , C25D3/62 , C25D3/64 , C25D5/10 , C25D5/12 , C25D5/50 , C25D7/12 , C25D5/00
CPC分类号： H01L31/022433 , C25D3/38 , C25D3/56 , C25D3/562 , C25D3/567 , C25D3/58 , C25D3/60 , C25D3/62 , C25D3/64 , C25D5/006 , C25D5/10 , C25D5/12 , C25D5/50 , C25D7/12 , H01L21/2885 , H01L21/76841 , H01L23/53238 , H01L31/02168 , H01L31/022425 , H01L31/068 , H01L31/1864 , H01L2924/0002 , Y02E10/50 , H01L2924/00
摘要： A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.
摘要翻译：提供了包含含有金属磷层作为扩散阻挡层的含铜网状金属化结构的太阳能电池等太阳能电池。含铜网格金属化结构从底部到顶部包括不包括位于半导体衬底的前侧表面上的栅格图案内的铜或铜合金的电镀金属磷层，以及电镀铜 - 含有层。还提供了一种形成这种结构的方法。

7. 发明申请

US20120329200A1 SILICON SURFACE TEXTURING METHOD FOR REDUCING SURFACE REFLECTANCE 失效
标题翻译：用于减少表面反射的硅表面纹理方法
公开(公告)号：US20120329200A1
公开(公告)日：2012-12-27
申请号：US13165339
申请日：2011-06-21
申请人： Mahadevaiyer Krishnan , Jun Liu , Satyavolu S. Papa Rao , George G. Totir
发明人： Mahadevaiyer Krishnan , Jun Liu , Satyavolu S. Papa Rao , George G. Totir
IPC分类号： H01L31/18 , C09K13/02 , C09K13/00 , B82Y30/00
CPC分类号： H01L31/03845 , B82Y30/00 , C09K13/02 , H01L31/02363 , H01L31/1804 , H01L31/186 , Y02E10/547 , Y02P70/521
摘要： A method of texturing a surface of a crystalline silicon substrate is provided. The method includes immersing a crystalline silicon substrate into an aqueous alkaline etchant solution to form a pyramid shaped textured surface, with (111) faces exposed, on the crystalline silicon substrate. The aqueous alkaline etchant solution employed in the method of the present disclosure includes an alkaline component and a nanoparticle slurry component. Specifically, the aqueous alkaline etchant solution of the present disclosure includes 0.5 weight percent to 5 weight percent of an alkaline component and from 0.1 weight percent to 5 weight percent of a nanoparticle slurry on a dry basis.
摘要翻译：提供了一种纹理化晶体硅衬底表面的方法。该方法包括将晶体硅衬底浸入碱性蚀刻剂水溶液中，以形成在晶体硅衬底上（111）面暴露的金字塔形纹理表面。用于本公开方法的碱性蚀刻剂水溶液包括碱性组分和纳米颗粒淤浆组分。具体地说，本公开的碱性蚀刻剂水溶液包含0.5重量％至5重量％的碱性组分和0.1重量％至5重量％的基于干基的纳米颗粒浆料。

8. 发明授权

US07969274B2 Method to improve inductance with a high-permeability slotted plate core in an integrated circuit 有权
标题翻译：在集成电路中用高磁导率开槽板芯改善电感的方法
公开(公告)号：US07969274B2
公开(公告)日：2011-06-28
申请号：US12202665
申请日：2008-09-02
申请人： Kenneth D. Brennan , Satyavolu S. Papa Rao , Byron Williams
发明人： Kenneth D. Brennan , Satyavolu S. Papa Rao , Byron Williams
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01F2017/008 , H01L2924/0002 , H01L2924/3011 , Y10T29/49073 , H01L2924/00
摘要： An inductor structure (102) formed in an integrated circuit (100) is disclosed, and includes a first isolation layer (106) and a first core plate (104) disposed over or within the first isolation layer (106, 114). The first core plate (104) includes a plurality of electrically coupled conductive traces composed of a conductive ferromagnetic material layer. A second isolation layer (108) overlies the first isolation layer and an inductor coil (102) composed of a conductive material layer (118) is formed within the second isolation layer (108). Another core plate may be formed over the coil. The one or more core plates increase an inductance (L) of the inductor coil (102).
摘要翻译：公开了一种形成在集成电路（100）中的电感器结构（102），并且包括设置在第一隔离层（106,114）上或第一隔离层（106,114）内的第一隔离层（106）和第一芯板（104）。第一芯板（104）包括由导电铁磁材料层构成的多个电耦合导电迹线。第二隔离层（108）覆盖第一隔离层，并且在第二隔离层（108）内形成由导电材料层（118）构成的电感线圈（102）。可以在线圈上形成另一个芯板。一个或多个芯板增加电感线圈（102）的电感（L）。

9. 发明授权

US07179747B2 Use of supercritical fluid for low effective dielectric constant metallization 有权
标题翻译：超临界流体用于低有效介电常数金属化
公开(公告)号：US07179747B2
公开(公告)日：2007-02-20
申请号：US10902243
申请日：2004-07-28
申请人： Satyavolu S. Papa Rao , Stephan Grunow , Phillip D. Matz
发明人： Satyavolu S. Papa Rao , Stephan Grunow , Phillip D. Matz
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01L23/5329 , H01L21/31116 , H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.
摘要翻译：本发明的实施例是一种制造集成电路的方法。该方法包括形成后端结构的覆盖层（步骤706），将覆盖层从提覆层钻到金属间介电层（步骤708），执行超临界流体处理以去除金属间的部分电介质层，其与所述提取线耦合（步骤710）：由此形成裸露的电介质区域。本发明的另一实施例是具有耦合到前端结构4的后端结构5的集成电路2.具有第一金属层22的后端结构5.具有金属互连15的第一金属级22和金属间介电层19.后端结构5还包含抽出线24和耦合到提取线24的裸露介质区25。

10. 发明授权

US08969122B2 Processes for uniform metal semiconductor alloy formation for front side contact metallization and photovoltaic device formed therefrom 有权
标题翻译：用于前侧接触金属化的均匀金属半导体合金形成工艺和由其形成的光电器件
公开(公告)号：US08969122B2
公开(公告)日：2015-03-03
申请号：US13159897
申请日：2011-06-14
申请人： Kathryn C. Fisher , Qiang Huang , Satyavolu S. Papa Rao , David L. Rath
发明人： Kathryn C. Fisher , Qiang Huang , Satyavolu S. Papa Rao , David L. Rath
IPC分类号： H01L31/18 , H01L31/0216 , H01L31/0224
CPC分类号： H01L31/02168 , H01L31/0201 , H01L31/0216 , H01L31/02167 , H01L31/022425 , H01L31/022433 , H01L31/18 , H01L31/1864 , Y02E10/50
摘要： Processes for fabricating photovoltaic devices in which the front side contact metal semiconductor alloy metallization patterns have a uniform thickness at edge portions as well as a central portion of each metallization pattern are provided. In one embodiment, a method of forming a photovoltaic device is provided that includes a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other, wherein an upper exposed surface of one of the semiconductor portions represents a front side surface of the semiconductor substrate; forming a plurality of patterned antireflective coating layers on the front side surface of the semiconductor surface to provide a grid pattern including a busbar region and finger regions; forming a mask atop the plurality of patterned antireflective coating layers, the mask having a shape that mimics each patterned antireflective coating; electrodepositing a metal layer on the busbar region and the finger regions; removing the mask; and performing an anneal, wherein during the anneal metal atoms from the metal layer react with semiconductor atoms from the busbar region and the finger regions forming a metal semiconductor alloy.
摘要翻译：提供了其中前侧接触金属半导体合金金属化图案在边缘部分具有均匀厚度以及每个金属化图案的中心部分的光伏器件的制造方法。在一个实施例中，提供了一种形成光伏器件的方法，该方法包括：pn结与p型半导体部分和n型半导体部分之间，其中一个半导体部分的上部暴露表面表示半导体衬底的前侧表面; 在所述半导体表面的前侧表面上形成多个图案化的抗反射涂层，以提供包括汇流条区域和手指区域的网格图案; 在所述多个图案化的抗反射涂层之上形成掩模，所述掩模具有模仿每个图案化抗反射涂层的形状; 在母线区域和手指区域上电沉积金属层; 去除面膜; 并执行退火，其中在退火期间，来自金属层的金属原子与母线区域的半导体原子和形成金属半导体合金的指状区域反应。

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