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    • 2. 发明申请
    • IC chip, board, information processing equipment and storage medium
    • IC芯片,板,信息处理设备和存储介质
    • US20070005512A1
    • 2007-01-04
    • US11355086
    • 2006-02-16
    • Naoki NishiguchiEiji Hasegawa
    • Naoki NishiguchiEiji Hasegawa
    • H04L9/00
    • G06F21/72G06Q20/3829H04L9/0891H04L9/0897H04L2209/60
    • An IC chip, a board, information processing equipment, and a storage medium are provided that can prevent, even when information is transferred between a plurality of programs, leaking of the right protection algorithm of information in connection with the transfer. A security board is included an IC chip having a secure module. The secure module receives an encryption key request signal, and generates a communication encryption key every time when the encryption key request signal is received, the communication encryption key being used to encrypt information to be transferred between a plurality of programs. The number of times the communication encryption key is supplied is counted. If the counted number is equal to or less than a predetermined number, the communication encryption key is supplied to outside. If the counted number exceeds the predetermined number, the supply of the generated communication encryption key to outside is stopped.
    • 提供了一种IC芯片,电路板,信息处理设备和存储介质,即使当在多个程序之间传送信息时,也可以防止与传送有关的信息的右侧保护算法泄漏。 安全板包括具有安全模块的IC芯片。 安全模块接收加密密钥请求信号,并且每当接收到加密密钥请求信号时生成通信加密密钥,该通信加密密钥用于加密要在多个程序之间传送的信息。 计算提供通信加密密钥的次数。 如果计数的数量等于或小于预定数量,则将通信加密密钥提供给外部。 如果计数的数量超过预定数量,则停止将生成的通信加密密钥提供给外部。
    • 3. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20060226454A1
    • 2006-10-12
    • US11401292
    • 2006-04-11
    • Mitsuhiro TogoEiji Hasegawa
    • Mitsuhiro TogoEiji Hasegawa
    • H01L29/76H01L29/94H01L31/00
    • H01L29/4916H01L21/28035H01L21/82345H01L21/823456
    • A semiconductor device 1 according to the present invention includes a semiconductor substrate 5, a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first gate electrode portion 16 constituted by a first gate insulating film 24 and a first gate electrode 26 having a first gate length L1 which are stacked, and a second transistor 12 which is formed on the semiconductor substrate 5 and includes a second gate electrode portion 20 constituted by a second gate insulating film 32 and a second gate electrode 30 having a second gate length L2 smaller than the first gate length L1, the second gate insulating film 32 and the second gate electrode 30 being stacked, wherein the grain size of poly-silicon grains forming the first gate electrode 26 is greater than the grain size of poly-silicon grains forming the second gate electrode 30.
    • 根据本发明的半导体器件1包括半导体衬底5,第一晶体管10,其形成在半导体衬底5上,并且包括由第一栅极绝缘膜24和第一栅电极26构成的第一栅电极部分16, 堆叠的第一栅极长度L 1和形成在半导体衬底5上并包括由第二栅极绝缘膜32和第二栅极电极30构成的第二栅极电极部分20的第二晶体管12,第二栅极电极30具有第二栅极长度 L 2,第二栅极绝缘膜32和第二栅电极30堆叠,其中形成第一栅电极26的多晶硅颗粒的晶粒尺寸大于聚硅晶粒的晶粒尺寸, 形成第二栅电极30的硅晶粒。
    • 7. 发明授权
    • Method of manufacturing a semiconductor device
    • 制造半导体器件的方法
    • US08440521B2
    • 2013-05-14
    • US13067788
    • 2011-06-27
    • Naomi FukumakiEiji HasegawaToshihiro IizukaIchiro Yamamoto
    • Naomi FukumakiEiji HasegawaToshihiro IizukaIchiro Yamamoto
    • H01L21/3105
    • H01L21/823857H01L21/823842
    • A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained.
    • 制造具有p型场效应晶体管和n型场效应晶体管的半导体器件的方法包括以下步骤:按照所述顺序在衬底上形成界面绝缘层和高电容率层; 在高电介质层上形成牺牲层的图案; 在形成有牺牲层的第一区域和形成牺牲层的第二区域的高介电常数层上形成含有金属元素的含金属膜; 通过进行热处理,将金属元素引入第二区域中的界面绝缘层与高电容率层之间的界面; 并且通过湿法蚀刻去除牺牲层,其中在去除步骤中,牺牲层比高介电常数层容易蚀刻。 由此,能够获得可靠性优异的半导体装置。
    • 9. 发明授权
    • MOS Devices with different gate lengths and different gate polysilicon grain sizes
    • 具有不同栅极长度和不同栅极多晶硅晶粒尺寸的MOS器件
    • US07355256B2
    • 2008-04-08
    • US11401292
    • 2006-04-11
    • Mitsuhiro TogoEiji Hasegawa
    • Mitsuhiro TogoEiji Hasegawa
    • H01L29/78
    • H01L29/4916H01L21/28035H01L21/82345H01L21/823456
    • A semiconductor device 1 according to the present invention includes a semiconductor substrate 5, a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first gate electrode portion 16 constituted by a first gate insulating film 24 and a first gate electrode 26 having a first gate length L1 which are stacked, and a second transistor 12 which is formed on the semiconductor substrate 5 and includes a second gate electrode portion 20 constituted by a second gate insulating film 32 and a second gate electrode 30 having a second gate length L2 smaller than the first gate length L1, the second gate insulating film 32 and the second gate electrode 30 being stacked, wherein the grain size of poly-silicon grains forming the first gate electrode 26 is greater than the grain size of poly-silicon grains forming the second gate electrode 30.
    • 根据本发明的半导体器件1包括半导体衬底5,第一晶体管10,其形成在半导体衬底5上,并且包括由第一栅极绝缘膜24和第一栅电极26构成的第一栅电极部分16, 堆叠的第一栅极长度L 1和形成在半导体衬底5上并包括由第二栅极绝缘膜32和第二栅极电极30构成的第二栅极电极部分20的第二晶体管12,第二栅极电极30具有第二栅极长度 L 2,第二栅极绝缘膜32和第二栅电极30堆叠,其中形成第一栅电极26的多晶硅颗粒的晶粒尺寸大于聚硅晶粒的晶粒尺寸, 形成第二栅电极30的硅晶粒。