专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070003881A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070003881A1
公开(公告)日：2007-01-04
申请号：US11453087
申请日：2006-06-15
申请人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
发明人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
IPC分类号： G03F7/26
CPC分类号： G03F7/0035 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.
摘要翻译：一种制造半导体器件的方法包括在下面的区域上形成以第一间距布置的多个虚拟线图案，形成具有形成在虚拟线图案的长边上的预定掩模部分的第一掩模图案，每个第一掩模图案具有闭环形状并且围绕每个虚拟线图案，去除虚拟线图案，形成具有第一图案部分的第二掩模图案，该第一图案部分覆盖第一掩模图案的端部和位于相邻的第一掩模图案的端部之间的端部部分端部，使用第一掩模图案和第二掩模图案作为掩模蚀刻下面的区域，以形成各自位于相邻的预定掩模部分之间的沟槽，并且用预定的材料填充沟槽。

2. 发明授权

US07811745B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07811745B2
公开(公告)日：2010-10-12
申请号：US11453087
申请日：2006-06-15
申请人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
发明人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
IPC分类号： H01L21/00
CPC分类号： G03F7/0035 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.
摘要翻译：一种制造半导体器件的方法包括在下面的区域上形成以第一间距布置的多个虚拟线图案，形成具有形成在虚拟线图案的长边上的预定掩模部分的第一掩模图案，每个第一掩模图案具有闭环形状并且围绕每个虚拟线图案，去除虚拟线图案，形成具有第一图案部分的第二掩模图案，该第一图案部分覆盖第一掩模图案的端部和位于相邻的第一掩模图案的端部之间的端部部分端部，使用第一掩模图案和第二掩模图案作为掩模蚀刻下面的区域，以形成各自位于相邻的预定掩模部分之间的沟槽，并且用预定的材料填充沟槽。

3. 发明申请

US20060194429A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060194429A1
公开(公告)日：2006-08-31
申请号：US11317028
申请日：2005-12-27
申请人： Koji Hashimoto , Eiji Ito , Tetsuya Kamigaki , Hideyuki Kinoshita
发明人： Koji Hashimoto , Eiji Ito , Tetsuya Kamigaki , Hideyuki Kinoshita
IPC分类号： H01L21/4763
CPC分类号： H01L27/105 , H01L23/528 , H01L27/1052 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising a plurality of first wirings provided in a predetermined layer on a substrate with being lined up, and formed to extend longer or contract shorter from one side toward the other side along a direction in which the first wirings are lined up, adjacent one-end portions of the first wirings being arranged in positions displaced from one another in a direction crossing at right angles the direction in which the first wirings are lined up.
摘要翻译：一种半导体器件，包括设置在衬底上的预定层中的多个第一布线，其被排成一列，并且形成为沿着第一布线排列的方向从一侧向另一侧延伸较长或缩短，相邻第一布线的一端部布置在与第一布线排列方向成直角交叉的方向上彼此偏移的位置。

4. 发明授权

US08705261B2 Semiconductor device having dummy bit lines wider than bit lines 有权
标题翻译：具有比位线宽的虚拟位线的半导体器件
公开(公告)号：US08705261B2
公开(公告)日：2014-04-22
申请号：US13560137
申请日：2012-07-27
申请人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
发明人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
IPC分类号： G11C5/06
CPC分类号： G03F7/0035 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.
摘要翻译：一种制造半导体器件的方法包括在下面的区域上形成以第一间距布置的多个虚拟线图案，形成具有形成在虚拟线图案的长边上的预定掩模部分的第一掩模图案，每个第一掩模图案具有闭环形状并且围绕每个虚拟线图案，去除虚拟线图案，形成具有第一图案部分的第二掩模图案，该第一图案部分覆盖第一掩模图案的端部和位于相邻的第一掩模图案的端部之间的端部部分端部，使用第一掩模图案和第二掩模图案作为掩模蚀刻下面的区域，以形成各自位于相邻的预定掩模部分之间的沟槽，并且用预定的材料填充沟槽。

5. 发明授权

US07675161B2 Semiconductor device with wirings having varying lengths 失效
标题翻译：具有不同长度的布线的半导体器件
公开(公告)号：US07675161B2
公开(公告)日：2010-03-09
申请号：US11317028
申请日：2005-12-27
申请人： Koji Hashimoto , Eiji Ito , Tetsuya Kamigaki , Hideyuki Kinoshita
发明人： Koji Hashimoto , Eiji Ito , Tetsuya Kamigaki , Hideyuki Kinoshita
IPC分类号： H01L23/12 , H01L21/4763 , H05K1/11
CPC分类号： H01L27/105 , H01L23/528 , H01L27/1052 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising a plurality of first wirings provided in a predetermined layer on a substrate with being lined up, and formed to extend longer or contract shorter from one side toward the other side along a direction in which the first wirings are lined up, adjacent one-end portions of the first wirings being arranged in positions displaced from one another in a direction crossing at right angles the direction in which the first wirings are lined up.
摘要翻译：一种半导体器件，包括设置在衬底上的预定层中的多个第一布线，其被排成一列，并且形成为沿着第一布线排列的方向从一侧向另一侧延伸较长或缩短，相邻第一布线的一端部布置在与第一布线排列方向成直角交叉的方向上彼此偏移的位置。

6. 发明授权

US07604926B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07604926B2
公开(公告)日：2009-10-20
申请号：US11346237
申请日：2006-02-03
申请人： Tetsuya Kamigaki , Eiji Ito , Koji Hashimoto , Hideyuki Kinoshita
发明人： Tetsuya Kamigaki , Eiji Ito , Koji Hashimoto , Hideyuki Kinoshita
IPC分类号： G03F7/26
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A method of manufacturing a semiconductor device, comprises forming a first mask pattern on an under-layer region, forming a plurality of dummy-line patterns on the under-layer region, the dummy-line patterns being arranged at a first pitch, forming second mask patterns having mask parts provided on long sides of the dummy-line patterns, removing the dummy-line patterns, and etching the under-layer region by using the first mask pattern and the mask parts as a mask.
摘要翻译：一种制造半导体器件的方法，包括在下层区域上形成第一掩模图案，在下层区域上形成多个伪线图案，虚设图案以第一间距排列，形成第二掩模图案掩模图案具有设置在虚拟线图案的长边上的掩模部分，去除伪线图案，并且通过使用第一掩模图案和掩模部分作为掩模来蚀刻底层区域。

7. 发明申请

US20120292764A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120292764A1
公开(公告)日：2012-11-22
申请号：US13560137
申请日：2012-07-27
申请人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
发明人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
IPC分类号： H01L23/50
CPC分类号： G03F7/0035 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.
摘要翻译：一种制造半导体器件的方法包括在下面的区域上形成以第一间距布置的多个虚拟线图案，形成具有形成在虚拟线图案的长边上的预定掩模部分的第一掩模图案，每个第一掩模图案具有闭环形状并且围绕每个虚拟线图案，去除虚拟线图案，形成具有第一图案部分的第二掩模图案，该第一图案部分覆盖第一掩模图案的端部和位于相邻的第一掩模图案的端部之间的端部部分端部，使用第一掩模图案和第二掩模图案作为掩模蚀刻下面的区域，以形成各自位于相邻的预定掩模部分之间的沟槽，并且用预定的材料填充沟槽。

8. 发明授权

US08254154B2 NAND flash memory having bit line with smaller width than width of peripheral interconnect line 有权
标题翻译： NAND闪存具有比外围互连线的宽度小的宽度的位线
公开(公告)号：US08254154B2
公开(公告)日：2012-08-28
申请号：US12923309
申请日：2010-09-14
申请人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
发明人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
IPC分类号： G11C5/06
CPC分类号： G03F7/0035 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.
摘要翻译：一种制造半导体器件的方法包括在下面的区域上形成以第一间距布置的多个虚拟线图案，形成具有形成在虚拟线图案的长边上的预定掩模部分的第一掩模图案，每个第一掩模图案具有闭环形状并且围绕每个虚拟线图案，去除虚拟线图案，形成具有第一图案部分的第二掩模图案，该第一图案部分覆盖第一掩模图案的端部和位于相邻的第一掩模图案的端部之间的端部部分端部，使用第一掩模图案和第二掩模图案作为掩模蚀刻下面的区域，以形成各自位于相邻的预定掩模部分之间的沟槽，并且用预定的材料填充沟槽。

9. 发明申请

US20110006424A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110006424A1
公开(公告)日：2011-01-13
申请号：US12923309
申请日：2010-09-14
申请人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
发明人： Eiji Ito , Hideyuki Kinoshita , Tetsuya Kamigaki , Koji Hashimoto
IPC分类号： H01L23/532
CPC分类号： G03F7/0035 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.
摘要翻译：一种制造半导体器件的方法包括在下面的区域上形成以第一间距布置的多个虚拟线图案，形成具有形成在虚拟线图案的长边上的预定掩模部分的第一掩模图案，每个第一掩模图案具有闭环形状并且围绕每个虚拟线图案，去除虚拟线图案，形成具有第一图案部分的第二掩模图案，该第一图案部分覆盖第一掩模图案的端部和位于相邻的第一掩模图案的端部之间的端部部分端部，使用第一掩模图案和第二掩模图案作为掩模蚀刻下面的区域，以形成各自位于相邻的预定掩模部分之间的沟槽，并且用预定的材料填充沟槽。

10. 发明申请

US20060234165A1 Method of manufacturing a semiconductor device 有权
公开(公告)号：US20060234165A1
公开(公告)日：2006-10-19
申请号：US11346237
申请日：2006-02-03
申请人： Tetsuya Kamigaki , Eiji Ito , Koji Hashimoto , Hideyuki Kinoshita
发明人： Tetsuya Kamigaki , Eiji Ito , Koji Hashimoto , Hideyuki Kinoshita
IPC分类号： G03F7/26
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A method of manufacturing a semiconductor device, comprises forming a first mask pattern on an under-layer region, forming a plurality of dummy-line patterns on the under-layer region, the dummy-line patterns being arranged at a first pitch, forming second mask patterns having mask parts provided on long sides of the dummy-line patterns, removing the dummy-line patterns, and etching the under-layer region by using the first mask pattern and the mask parts as a mask.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式