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1. 发明授权

US10366981B2 Power semiconductor devices 有权
公开(公告)号：US10366981B2
公开(公告)日：2019-07-30
申请号：US14845939
申请日：2015-09-04
申请人： FAIRCHILD KOREA SEMICONDUCTOR LTD.
发明人： Sun-hak Lee , Yong Zhong Hu , Hye-mi Kim
IPC分类号： H01L27/06 , H01L29/06 , H01L29/10 , H01L29/66 , H01L29/808 , H01L29/861
摘要： A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate. The diode part includes a p-type body region disposed inside the substrate and electrically connected with the anode terminal, an n-type well disposed on one side of the p-type body region and having a first impurity concentration, and a first n-type semiconductor region disposed below the p-type body region and having a second impurity concentration which is lower than the first impurity concentration.

2. 发明授权

US09257502B2 Level shift power semiconductor device 有权
标题翻译：电平变换功率半导体器件
公开(公告)号：US09257502B2
公开(公告)日：2016-02-09
申请号：US13928186
申请日：2013-06-26
申请人： Fairchild Korea Semiconductor Ltd.
发明人： Min-suk Kim , Sun-hak Lee , Jin-woo Moon , Hye-mi Kim
IPC分类号： H01L29/78 , H01L29/772 , H01L29/06 , H01L29/40 , H01L29/66 , H01L29/739
CPC分类号： H01L29/063 , H01L29/402 , H01L29/66325 , H01L29/7393
摘要： In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate.
摘要翻译：在一个一般方面，功率半导体器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的第二导电类型的半导体层。半导体层可以包括高压单元，设置在高压单元周围的低电压单元，以及设置在高压单元和低压单元之间的电平移位单元。功率半导体器件可以包括布置在高压单元和电平移位单元之间的第一导电类型的第一隔离区域和布置在低压单元和电平移位单元之间的第一导电类型的第二隔离区域，其中第一隔离区域和第二隔离区域各自在半导体层中垂直对准，并且各自延伸至至少半导体衬底。

3. 发明授权

US09947742B2 Power semiconductor device 有权
公开(公告)号：US09947742B2
公开(公告)日：2018-04-17
申请号：US15337748
申请日：2016-10-28
申请人： FAIRCHILD KOREA SEMICONDUCTOR LTD.
发明人： Hye-mi Kim , Sun-hak Lee
IPC分类号： H01L29/06 , H01L27/08 , H01L29/861 , H01L29/40 , H01L29/66 , H01L27/06
CPC分类号： H01L29/0642 , H01L27/0629 , H01L29/402 , H01L29/66136 , H01L29/861
摘要： A power semiconductor device includes: a substrate; an anode electrode and a cathode electrode disposed on the substrate; a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity; an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration; and an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.

4. 发明申请

US20170148873A1 POWER SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20170148873A1
公开(公告)日：2017-05-25
申请号：US15337748
申请日：2016-10-28
申请人： FAIRCHILD KOREA SEMICONDUCTOR LTD.
发明人： Hye-mi Kim , Sun-hak Lee
IPC分类号： H01L29/06 , H01L27/08 , H01L29/36 , H01L29/861 , H01L29/417
CPC分类号： H01L29/0642 , H01L27/0629 , H01L29/402 , H01L29/66136 , H01L29/861
摘要： A power semiconductor device includes: a substrate; an anode electrode and a cathode electrode disposed on the substrate; a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity; an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration; and an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.

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