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1. 发明授权

US09331092B2 Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays 有权
公开(公告)号：US09331092B2
公开(公告)日：2016-05-03
申请号：US14706130
申请日：2015-05-07
申请人： Freescale Semiconductor, Inc.
发明人： Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang
IPC分类号： H01L29/788 , H01L27/115 , H01L29/423
CPC分类号： H01L27/11568 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.

2. 发明授权

US10026820B2 Split gate device with doped region and method therefor 有权
公开(公告)号：US10026820B2
公开(公告)日：2018-07-17
申请号：US15078860
申请日：2016-03-23
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Weize Chen , Cheong Min Hong , Konstantin V. Loiko , Jane A. Yater
IPC分类号： H01L29/423 , H01L27/11521 , H01L27/11568 , H01L21/8234
摘要： A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.

3. 发明申请

US20150236035A1 Methods For Forming Contact Landing Regions In Split-Gate Non-Volatile Memory (NVM) Cell Arrays 有权
标题翻译：用于在分离门非易失性存储器（NVM）单元阵列中形成接触着陆区域的方法
公开(公告)号：US20150236035A1
公开(公告)日：2015-08-20
申请号：US14706130
申请日：2015-05-07
申请人： Freescale Semiconductor, Inc.
发明人： Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L27/11568 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.
摘要翻译：公开了用于在分闸NVM（非易失性存储器）系统中形成接触着陆区域的方法和相关结构。形成虚拟选择栅结构，同时形成分闸NVM单元的选择栅极。在选择栅极和虚拟选择栅极结构上形成控制栅极层，以及中间电荷存储层。控制栅极材料将填充选择栅极材料和虚拟选择栅极材料之间的间隙。然后使用非图案化间隔物蚀刻来蚀刻控制栅极层以形成与虚拟选择栅极结构相关联的接触着色区域，同时还形成用于分离栅极NVM单元的间隔物控制栅极。所公开的实施例提供改进的（例如更平坦的）接触着陆区域，而不需要额外的处理步骤，而不增加所得到的NVM单元阵列的间距。

4. 发明申请

US20150054044A1 Method to Form a Polysilicon Nanocrystal Thin Film Storage Bitcell within a High K Metal Gate Platform Technology Using a Gate Last Process to Form Transistor Gates 有权
标题翻译：在高K金属栅极平台技术中形成多晶硅纳米晶体薄膜存储位元的方法使用栅极最后工艺形成晶体管栅极
公开(公告)号：US20150054044A1
公开(公告)日：2015-02-26
申请号：US13973433
申请日：2013-08-22
申请人： Freescale Semiconductor, Inc
发明人： Asanga H. Perera , Sung-Taeg Kang , Jane A. Yater , Cheong Min Hong
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L21/28273 , H01L27/11534 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/7881
摘要： A process integration is disclosed for fabricating non-volatile memory (NVM) cells (105-109, 113-115) on a first flash cell substrate area (111) which are encapsulated in one or more planar dielectric layers (116) prior to forming an elevated substrate (117) on a second CMOS transistor area (112) on which high-k metal gate electrodes (119-120, 122-126, 132, 134) are formed using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.
摘要翻译：公开了一种用于在第一闪存单元衬底区域（111）上制造非易失性存储器（NVM）单元（105-109,113-115）的工艺集成，其在形成之前封装在一个或多个平面介电层（116）中在第二CMOS晶体管区域（112）上的升高的衬底（117），其上使用最后HKMG CMOS工艺流程形成高k金属栅电极（119-120,122-126,132,134），而不干扰 NVM单元的操作或可靠性。

5. 发明申请

US20160300919A1 METHOD OF FORMING SPLIT GATE MEMORY WITH IMPROVED RELIABILITY 有权
标题翻译：形成具有改进的可靠性的分离器存储器的方法
公开(公告)号：US20160300919A1
公开(公告)日：2016-10-13
申请号：US15183202
申请日：2016-06-15
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Cheong Min HONG , Konstantin V. Loiko , Jane A. Yater
IPC分类号： H01L29/423 , H01L29/08 , H01L29/792 , H01L29/66 , H01L29/788 , H01L21/265 , H01L29/10
CPC分类号： H01L29/42328 , H01L21/26513 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： A first doped region extends from a top surface of a substrate to a first depth. An implant into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.
摘要翻译：第一掺杂区域从衬底的顶表面延伸到第一深度。在第一掺杂区域中的注入形成第二导电类型的第二掺杂区域。第二掺杂区域从顶表面延伸到小于第一深度的第二深度。分裂门NVM结构在第二掺杂区域上具有选择和控制栅极。形成与选择栅极相邻的第二导电类型的漏极区域。第二导电类型的源极区域形成为与控制栅极相邻。进入第二掺杂区域的倾斜植入物形成在选择栅极的一部分下的第一导电类型的第三掺杂区域和在控制栅极的一部分下的第一导电类型的第四掺杂区域。漏极和源极区域与第三和第四区域相邻。

6. 发明授权

US09129855B2 Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology 有权
标题翻译：非易失性存储器（NVM）和高k和金属门集成使用门控方法
公开(公告)号：US09129855B2
公开(公告)日：2015-09-08
申请号：US14041647
申请日：2013-09-30
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Asanga H. Perera , Cheong Min Hong , Sung-Taeg Kang , Jane A. Yater
IPC分类号： H01L21/336 , H01L27/115 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/788
CPC分类号： H01L27/11524 , H01L21/28282 , H01L27/11529 , H01L27/11534 , H01L29/42332 , H01L29/66825 , H01L29/7833 , H01L29/7887
摘要： A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.
摘要翻译：制造半导体结构的方法包括在NVM部分的衬底上形成选择栅极，在逻辑部分上形成第一保护层。在NVM部分中的衬底上形成控制栅极和存储层，其中控制和选择栅极具有共面的顶表面。电荷存储层位于控制栅极下方，沿着选择栅极和控制栅极的相邻侧壁，并且部分地位于选择栅极的顶表面上。在NVM部分和逻辑部分上形成第二保护层。从逻辑部分去除第二保护层和第一保护层，留下第二保护层的一部分在控制栅极和选择栅极上。在包括高k电介质和金属栅极的逻辑部分上形成栅极结构。

7. 发明授权

US08901632B1 Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology 有权
标题翻译：非易失性存储器（NVM）和高K和金属门集成使用最后的方法
公开(公告)号：US08901632B1
公开(公告)日：2014-12-02
申请号：US14041662
申请日：2013-09-30
申请人： Freescale Semiconductor, Inc.
发明人： Asanga H. Perera , Cheong Min Hong , Sung-Taeg Kang , Byoung W. Min , Jane A. Yater
IPC分类号： H01L21/82 , H01L21/336 , H01L29/792 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7831 , H01L21/82 , H01L27/11534 , H01L27/11573 , H01L29/42328 , H01L29/42332 , H01L29/66484 , H01L29/66545
摘要： A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.
摘要翻译：制造半导体结构的方法包括在NVM区域上的衬底上形成选择栅极，在逻辑区域上形成第一保护层。在NVM区域中的衬底上形成控制栅极和存储层。控制门具有在选择门的顶表面下方的顶表面。电荷存储层位于控制栅极下方，沿着选择栅极和控制栅极的相邻侧壁，并且部分地位于选择栅极的顶表面上方。在NVM部分和逻辑部分上形成第二保护层。从逻辑区域移除第一和第二保护层。第二保护层的一部分留在控制栅极和选择栅极上。在逻辑区域上形成的栅极结构具有高k电介质和金属栅极。

8. 发明授权

US09397201B2 Non-volatile memory (NVM) cell and a method of making 有权
标题翻译：非易失性存储器（NVM）单元及其制造方法
公开(公告)号：US09397201B2
公开(公告)日：2016-07-19
申请号：US14943175
申请日：2015-11-17
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Jacob T. Williams , Cheong Min Hong , Sung-Taeg Kang , David G. Kolar , Jane A. Yater
IPC分类号： H01L29/66 , H01L29/792 , H01L21/3213 , H01L21/3105 , H01L21/321 , H01L29/423 , H01L21/28 , H01L29/788
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L21/31055 , H01L21/3212 , H01L21/32133 , H01L21/32139 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.
摘要翻译：形成闪存单元的方法包括在基板上形成第一硬掩模和第二硬掩模。选择栅极形成为围绕第一硬掩模的间隔物。在第一和第二硬掩模和选择栅极上形成电荷存储层。控制栅极形成为围绕第二硬掩模的间隔物。控制栅极中的凹槽填充有电介质材料。凹槽形成在控制栅极的弯曲侧壁和电荷存储层的与控制栅极的弯曲侧壁直接相邻的侧壁之间。

9. 发明授权

US09847397B2 Method of forming split gate memory with improved reliability 有权
公开(公告)号：US09847397B2
公开(公告)日：2017-12-19
申请号：US15183202
申请日：2016-06-15
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Cheong Min Hong , Konstantin V. Loiko , Jane A. Yater
IPC分类号： H01L29/41 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/66 , H01L21/265 , H01L29/10 , H01L29/08 , H01L21/8239
CPC分类号： H01L29/42328 , H01L21/26513 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： A first doped region extends from a top surface of a substrate to a first depth. An implant into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.

10. 发明申请

US20150091079A1 NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-FIRST METHODOLOGY 有权
标题翻译：非挥发性记忆（NVM）和高K和金属栅格整合使用盖茨第一方法
公开(公告)号：US20150091079A1
公开(公告)日：2015-04-02
申请号：US14041647
申请日：2013-09-30
申请人： Freescale Semiconductor, Inc.
发明人： ASANGA H. PERERA , Cheong Min Hong , Sung-Taeg Kang , Jane A. Yater
IPC分类号： H01L27/115
CPC分类号： H01L27/11524 , H01L21/28282 , H01L27/11529 , H01L27/11534 , H01L29/42332 , H01L29/66825 , H01L29/7833 , H01L29/7887
摘要： A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.
摘要翻译：制造半导体结构的方法包括在NVM部分的衬底上形成选择栅极，在逻辑部分上形成第一保护层。在NVM部分中的衬底上形成控制栅极和存储层，其中控制和选择栅极具有共面的顶表面。电荷存储层位于控制栅极下方，沿着选择栅极和控制栅极的相邻侧壁，并且部分地位于选择栅极的顶表面上。在NVM部分和逻辑部分上形成第二保护层。从逻辑部分去除第二保护层和第一保护层，留下第二保护层的一部分在控制栅极和选择栅极上。在包括高k电介质和金属栅极的逻辑部分上形成栅极结构。

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