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1. 发明申请

US20170033005A1 SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE 有权
标题翻译：具有沟槽形状的通孔的半导体器件
公开(公告)号：US20170033005A1
公开(公告)日：2017-02-02
申请号：US15291593
申请日：2016-10-12
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Kenichi Watanabe
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
摘要翻译：半导体器件具有形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽形通孔66a中的埋入导体70,72a。形成沟槽状的通孔66a的宽度小于孔状通孔66的宽度。可以防止埋入导体的填充不充分和层间绝缘膜的开裂。导体插头上的步骤可以减少。因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题。

2. 发明申请

US20140291864A1 SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE 有权
标题翻译：具有沟槽形状的通孔的半导体器件
公开(公告)号：US20140291864A1
公开(公告)日：2014-10-02
申请号：US14304225
申请日：2014-06-13
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Kenichi Watanabe
IPC分类号： H01L23/522
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
摘要翻译：半导体器件具有形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽形通孔66a中的埋入导体70,72a。形成沟槽状的通孔66a的宽度小于孔状通孔66的宽度。可以防止埋入导体的填充不充分和层间绝缘膜的开裂。导体插头上的步骤可以减少。因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题。

3. 发明申请

US20140291863A1 SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE 有权
公开(公告)号：US20140291863A1
公开(公告)日：2014-10-02
申请号：US14304186
申请日：2014-06-13
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Kenichi Watanabe
IPC分类号： H01L23/522
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

4. 发明授权

US08847403B2 Semiconductor device including two groove-shaped patterns 有权
标题翻译：半导体器件包括两个槽形图案
公开(公告)号：US08847403B2
公开(公告)日：2014-09-30
申请号：US13780396
申请日：2013-02-28
申请人： Fujitsu Semiconductor Limited
发明人： Kenichi Watanabe
IPC分类号： H01L23/528 , H01L23/532 , H01L23/485 , H01L29/06 , H01L23/522 , H01L23/58
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
摘要翻译：半导体器件具有形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽形通孔66a中的埋入导体70,72a。形成沟槽状的通孔66a的宽度小于孔状通孔66的宽度。可以防止埋入导体的填充不充分和层间绝缘膜的开裂。导体插头上的步骤可以减少。因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题。

5. 发明授权

US08841775B2 Semiconductor device having groove-shaped via-hole 有权
公开(公告)号：US08841775B2
公开(公告)日：2014-09-23
申请号：US13834418
申请日：2013-03-15
申请人： Fujitsu Semiconductor Limited
发明人： Kenichi Watanabe
IPC分类号： H01L23/522 , H01L23/485 , H01L29/06 , H01L23/528 , H01L23/58 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

6. 发明申请

US20140179098A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20140179098A1
公开(公告)日：2014-06-26
申请号：US14190567
申请日：2014-02-26
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Kenichi Watanabe , Nobuhiro Misawa
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76879 , H01L21/76808 , H01L23/5222 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provided between the plurality of interconnection layers and electrically interconnecting the plurality of the electrode patterns between the interconnection layers adjacent to each other, and an insulating films formed between the plurality of interconnection layers and the plurality of via parts. Each of the plurality of via parts is laid out, offset from a center of the electrode pattern in a second direction intersecting the first direction, and the plurality of electrode patterns has a larger line width at parts where the via parts are connected to, and a distance between the electrode patterns and the adjacent electrode patterns is reduced at the parts.
摘要翻译：该半导体器件包括：包括彼此堆叠的多个互连层的电容器，多个互连层各自包括沿第一方向延伸的多个电极图案;多个通孔部件，设置在多个互连层之间，并且电连接彼此相邻的互连层之间的多个电极图案，以及形成在多个互连层和多个通孔部之间的绝缘膜。多个通孔部分中的每一个在与第一方向相交的第二方向上布置成从电极图案的中心偏移，并且多个电极图案在通孔部分连接的部分具有较大的线宽，在这些部分，电极图案和相邻电极图案之间的距离减小。

7. 发明申请

US20140077392A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140077392A1
公开(公告)日：2014-03-20
申请号：US14085124
申请日：2013-11-20
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Kenichi Watanabe
IPC分类号： H01L23/522
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
摘要翻译：半导体器件具有形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽形通孔66a中的埋入导体70,72a。形成沟槽状的通孔66a的宽度小于孔状通孔66的宽度。可以防止埋入导体的填充不充分和层间绝缘膜的开裂。导体插头上的步骤可以减少。因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题。

8. 发明申请

US20130175691A1 SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE 有权
公开(公告)号：US20130175691A1
公开(公告)日：2013-07-11
申请号：US13780174
申请日：2013-02-28
申请人： Fujitsu Semiconductor Limited
发明人： Kenichi Watanabe
IPC分类号： H01L23/485
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

9. 发明申请

US20190385905A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD 审中-公开
公开(公告)号：US20190385905A1
公开(公告)日：2019-12-19
申请号：US16552600
申请日：2019-08-27
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Yasunori Uchino , Kenichi Watanabe
IPC分类号： H01L21/768 , H01L23/48 , G06F17/50 , H01L23/522 , H01L23/528
摘要： A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.

10. 发明授权

US09972531B2 Method of manufacturing a semiconductor device having groove-shaped via-hole 有权
公开(公告)号：US09972531B2
公开(公告)日：2018-05-15
申请号：US15291593
申请日：2016-10-12
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Kenichi Watanabe
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528 , H01L23/522 , H01L23/58 , H01L29/06 , H01L23/485 , H01L23/48 , H01L23/00
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

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