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1. 发明授权

US09123742B2 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US09123742B2
公开(公告)日：2015-09-01
申请号：US13783299
申请日：2013-03-03
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Masashi Shima
IPC分类号： H01L21/336 , H01L29/66 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78 , H01L21/265 , H01L29/45 , H01L29/49
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L29/1045 , H01L29/456 , H01L29/4933 , H01L29/66477 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region.
摘要翻译：一种制造半导体器件的方法包括在第一晶体管区域中的半导体衬底上形成第一栅电极; 形成通道剂量区域; 以及形成第一源极延伸区域，其中通过使用第一掩模作为掩模并且通过离子注入第一导电类型的第一掺杂剂形成沟道剂量区域，并且覆盖第一栅电极的漏极侧的第一掩模并且覆盖漏极区域，并且通过使用第二掩模和栅极电极作为掩模并且通过离子注入作为与第一导电类型相反的导电类型的第二导电类型的第二掺杂剂形成第一源极延伸区域，所述第二掩模覆盖所述第一栅电极的漏极侧并覆盖所述漏极区。

2. 发明授权

US08853673B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08853673B2
公开(公告)日：2014-10-07
申请号：US13894871
申请日：2013-05-15
申请人： Fujitsu Semiconductor Limited
发明人： Yosuke Shimamune , Akira Katakami , Akiyoshi Hatada , Masashi Shima , Naoyoshi Tamura
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/78 , H01L29/04 , H01L29/08 , H01L29/66 , H01L21/02 , H01L21/306 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/28518 , H01L21/30608 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/45 , H01L29/4975 , H01L29/518 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , Y10S257/90
摘要： A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
摘要翻译：一种半导体器件包括：栅极电极，形成在硅衬底上，栅极绝缘膜对应于沟道区，形成在硅衬底中的p型扩散区的源极和漏极区域的侧壁绝缘膜的相应外侧栅电极和在硅衬底中在与硅衬底呈外延角的侧壁绝缘膜的各外侧形成的一对SiGe混合晶体区域，SiGe混晶区域由彼此相对的侧壁表面限定，其中在每个SiGe混合晶体区域中，侧壁表面由相对于硅衬底的主表面形成相应不同角度的多个面限定。

3. 发明授权

US08735254B2 Manufacture method of a high voltage MOS semiconductor device 有权
标题翻译：高压MOS半导体器件的制造方法
公开(公告)号：US08735254B2
公开(公告)日：2014-05-27
申请号：US13779163
申请日：2013-02-27
申请人： Fujitsu Semiconductor Limited
发明人： Masashi Shima , Kazukiyo Joshin , Toshihide Suzuki
IPC分类号： H01L21/336
CPC分类号： H01L29/66681 , H01L21/26586 , H01L29/0634 , H01L29/0847 , H01L29/41775 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.
摘要翻译：半导体器件具有：在MIS型晶体管的栅电极下方的低浓度漏极区域; 高浓度漏区，其杂质浓度高于低浓度漏区，并形成在与栅电极间隔开的低浓度漏区中; 以及与在高浓度漏极区域和栅电极之间的表面积上形成的低浓度漏极区域中形成的漏极区域的导电类型相反的导电类型区域，形成pn的相反导电类型区域和低浓度漏极区域交界处

4. 发明授权

US08633075B2 Semiconductor device with high voltage transistor 有权
标题翻译：具有高压晶体管的半导体器件
公开(公告)号：US08633075B2
公开(公告)日：2014-01-21
申请号：US13797084
申请日：2013-03-12
申请人： Fujitsu Semiconductor Limited
发明人： Masashi Shima
IPC分类号： H01L21/8234
CPC分类号： H01L29/0653 , H01L21/26586 , H01L29/0847 , H01L29/105 , H01L29/1083 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A method for manufacturing a semiconductor includes: forming an isolation region defining first, second and third active regions; implanting first impurity ions of a first conductivity type to form first, second and third wells; implanting second impurity ions of the first conductivity type to form first and second channel regions; implanting second impurity ions of a second conductivity to form a first drain region, such that a portion of the first channel region is overlapped with the first drain region; forming first, second and third gate electrodes, the first gate electrode superposing a portion of the first drain region and covering one lateral end of the first channel region; forming first insulating side wall spacers and a second insulating side wall spacer on a side wall of the first gate electrode; and implanting fourth impurity ions of the second conductivity type to form second drain/source regions.
摘要翻译：一种制造半导体的方法包括：形成限定第一，第二和第三有源区的隔离区; 注入第一导电类型的第一杂质离子以形成第一，第二和第三阱; 注入第一导电类型的第二杂质离子以形成第一和第二沟道区; 注入具有第二导电性的第二杂质离子以形成第一漏区，使得第一沟道区的一部分与第一漏区重叠; 形成第一，第二和第三栅电极，所述第一栅电极叠加所述第一漏区的一部分并覆盖所述第一沟道区的一个侧端; 在所述第一栅电极的侧壁上形成第一绝缘侧壁间隔物和第二绝缘侧壁间隔物; 以及注入所述第二导电类型的第四杂质离子以形成第二漏极/源极区域。

5. 发明申请

US20140004673A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140004673A1
公开(公告)日：2014-01-02
申请号：US14017917
申请日：2013-09-04
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Masashi Shima
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L29/0847 , H01L29/1045 , H01L29/41 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device including a low-concentration impurity region formed on the drain side of an n-type MIS transistor, in a non-self-aligned manner with respect to an end portion of the gate electrode. A high-concentration impurity region is placed with a specific offset from the gate electrode and a sidewall insulating film. The semiconductor device enables the drain breakdown voltage to be sufficient and the on-resistance to decrease. A silicide layer is also formed on the surface of the gate electrode, thereby achieving gate resistance reduction and high frequency characteristics improvement.
摘要翻译：一种半导体器件，包括在n型MIS晶体管的漏极侧形成的相对于栅电极的端部以非自对准的方式形成的低浓度杂质区。高浓度杂质区域与栅电极和侧壁绝缘膜具有特定的偏移位置。半导体器件能够使漏极击穿电压足够并且导通电阻降低。在栅电极的表面上还形成硅化物层，从而实现栅极电阻降低和高频特性的改善。

6. 发明申请

US20130171791A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130171791A1
公开(公告)日：2013-07-04
申请号：US13779163
申请日：2013-02-27
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Masashi Shima , Kazukiyo Joshin , Toshihide Suzuki
IPC分类号： H01L29/66
CPC分类号： H01L29/66681 , H01L21/26586 , H01L29/0634 , H01L29/0847 , H01L29/41775 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.
摘要翻译：半导体器件具有：在MIS型晶体管的栅电极下方的低浓度漏极区域; 高浓度漏区，其杂质浓度高于低浓度漏区，并形成在与栅电极间隔开的低浓度漏区中; 以及与在高浓度漏极区域和栅电极之间的表面积上形成的低浓度漏极区域中形成的漏极区域的导电类型相反的导电类型区域，形成pn的相反导电类型区域和低浓度漏极区域交界处

7. 发明授权

US08741724B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08741724B2
公开(公告)日：2014-06-03
申请号：US13886745
申请日：2013-05-03
申请人： Fujitsu Semiconductor Limited
发明人： Masashi Shima
IPC分类号： H01L21/336
CPC分类号： H01L27/088 , H01L21/2652 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/1045 , H01L29/105 , H01L29/66537 , H01L29/6659
摘要： A semiconductor device includes first, second and isolation regions; a first insulating film and gate electrode formed over the first region; a second insulating film and gate electrode formed over the second region; a first sidewall formed on a side of the first gate electrode and a second sidewall formed on a side of the second gate electrode; first source and drain regions formed adjacent opposite sides of the first gate electrode; second source region adjacent to the one side of the first gate electrode and overlapping the first source region, an impurity concentration of the second source region being different from an impurity of the first source region; a second drain region overlapping the first drain region and overlapping the first gate electrode; and a metal silicide formed on the first source region and the first drain region.
摘要翻译：半导体器件包括第一，第二和隔离区域; 形成在所述第一区域上的第一绝缘膜和栅电极; 形成在所述第二区域上的第二绝缘膜和栅电极; 形成在所述第一栅电极的一侧上的第一侧壁和形成在所述第二栅电极的一侧上的第二侧壁; 形成在第一栅电极的相对侧的第一源区和漏区; 第二源极区域，与第一栅极电极的一侧相邻并且与第一源极区域重叠，第二源极区域的杂质浓度不同于第一源极区域的杂质; 与所述第一漏极区重叠并与所述第一栅电极重叠的第二漏区; 以及形成在所述第一源极区域和所述第一漏极区域上的金属硅化物。

8. 发明申请

US20130241005A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130241005A1
公开(公告)日：2013-09-19
申请号：US13886745
申请日：2013-05-03
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Masashi Shima
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/2652 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/1045 , H01L29/105 , H01L29/66537 , H01L29/6659
摘要： A semiconductor device includes first, second and isolation regions; a first insulating film and gate electrode formed over the first region; a second insulating film and gate electrode formed over the second region; a first sidewall formed on a side of the first gate electrode and a second sidewall formed on a side of the second gate electrode; first source and drain regions formed adjacent opposite sides of the first gate electrode; second source region adjacent to the one side of the first gate electrode and overlapping the first source region, an impurity concentration of the second source region being different from an impurity of the first source region; a second drain region overlapping the first drain region and overlapping the first gate electrode; and a metal silicide formed on the first source region and the first drain region.
摘要翻译：半导体器件包括第一，第二和隔离区域; 形成在所述第一区域上的第一绝缘膜和栅电极; 形成在所述第二区域上的第二绝缘膜和栅电极; 形成在所述第一栅电极的一侧上的第一侧壁和形成在所述第二栅电极的一侧上的第二侧壁; 形成在第一栅电极的相对侧的第一源区和漏区; 第二源极区域，与第一栅极电极的一侧相邻并且与第一源极区域重叠，第二源极区域的杂质浓度不同于第一源极区域的杂质; 与所述第一漏极区重叠并与所述第一栅电极重叠的第二漏区; 以及形成在所述第一源极区域和所述第一漏极区域上的金属硅化物。

9. 发明申请

US20140361340A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140361340A1
公开(公告)日：2014-12-11
申请号：US14468519
申请日：2014-08-26
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Yosuke Shimamune , Akira Katakami , Akiyoshi Hatada , Masashi Shima , Naoyoshi Tamura
IPC分类号： H01L29/78 , H01L29/08 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/28518 , H01L21/30608 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/45 , H01L29/4975 , H01L29/518 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , Y10S257/90
摘要： A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
摘要翻译：一种半导体器件包括：栅极电极，形成在硅衬底上，栅极绝缘膜对应于沟道区，形成在硅衬底中的p型扩散区的源极和漏极区域的侧壁绝缘膜的相应外侧栅电极和在硅衬底中在与硅衬底呈外延角的侧壁绝缘膜的各外侧形成的一对SiGe混合晶体区域，SiGe混晶区域由彼此相对的侧壁表面限定，其中在每个SiGe混合晶体区域中，侧壁表面由相对于硅衬底的主表面形成相应不同角度的多个面限定。

10. 发明申请

US20130189820A1 SEMICONDUCTOR DEVICE WITH HIGH VOLTAGE TRANSISTOR 有权
标题翻译：具有高电压晶体管的半导体器件
公开(公告)号：US20130189820A1
公开(公告)日：2013-07-25
申请号：US13797084
申请日：2013-03-12
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Masashi Shima
IPC分类号： H01L29/06
CPC分类号： H01L29/0653 , H01L21/26586 , H01L29/0847 , H01L29/105 , H01L29/1083 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A method for manufacturing a semiconductor includes: forming an isolation region defining first, second and third active regions; implanting first impurity ions of a first conductivity type to form first, second and third wells; implanting second impurity ions of the first conductivity type to form first and second channel regions; implanting second impurity ions of a second conductivity to form a first drain region, such that a portion of the first channel region is overlapped with the first drain region; forming first, second and third gate electrodes, the first gate electrode superposing a portion of the first drain region and covering one lateral end of the first channel region; forming first insulating side wall spacers and a second insulating side wall spacer on a side wall of the first gate electrode; and implanting fourth impurity ions of the second conductivity type to form second drain/source regions.
摘要翻译：一种制造半导体的方法包括：形成限定第一，第二和第三有源区的隔离区; 注入第一导电类型的第一杂质离子以形成第一，第二和第三阱; 注入第一导电类型的第二杂质离子以形成第一和第二沟道区; 注入具有第二导电性的第二杂质离子以形成第一漏区，使得第一沟道区的一部分与第一漏区重叠; 形成第一，第二和第三栅电极，所述第一栅电极叠加所述第一漏区的一部分并覆盖所述第一沟道区的一个侧端; 在所述第一栅电极的侧壁上形成第一绝缘侧壁间隔物和第二绝缘侧壁间隔物; 以及注入所述第二导电类型的第四杂质离子以形成第二漏极/源极区域。

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