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1. 发明授权

US07060558B2 Method for fabricating a field-effect transistor having a floating gate 失效
公开(公告)号：US07060558B2
公开(公告)日：2006-06-13
申请号：US10320950
申请日：2002-12-16
申请人： Franz Hofmann , Georg Tempel , Robert Strenz , Robert Wiesner
发明人： Franz Hofmann , Georg Tempel , Robert Strenz , Robert Wiesner
IPC分类号： H01L21/336 , H01L21/425 , H01L21/3205 , H01L21/44 , H01L21/469
CPC分类号： H01L21/28273 , H01L29/42384
摘要： In the course of a method for fabricating a field-effect transistor having a floating gate, a structure is formed which has uncovered sidewalls of a layer made of the material for forming the floating gate and which is exposed to an oxidizing atmosphere in order to coat the sidewalls. At the same time, other regions of the structure have an insulating oxide layer. At a point in time prior to the action of an oxidizing atmosphere, nitrogen is implanted into the material of the floating gate in a quantity that appreciably reduces the oxidation at the sidewalls thereof.

2. 发明授权

US07893519B2 Integrated circuit with conductive structures 有权
标题翻译：具有导电结构的集成电路
公开(公告)号：US07893519B2
公开(公告)日：2011-02-22
申请号：US12128336
申请日：2008-05-28
申请人： Franz Hofmann
发明人： Franz Hofmann
IPC分类号： H01L29/00
CPC分类号： H01L27/11521 , H01L27/11524
摘要： An integrated circuit includes an array of transistors and a number of wordlines, where individual ones of the wordlines are coupled to a number of the transistors in the array. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.
摘要翻译：集成电路包括晶体管阵列和多个字线，其中字线中的单个字线与阵列中的多个晶体管耦合。与字线绝缘的导电结构被布置在字线下方的层中，并且布置在晶体管之间。

3. 发明授权

US07767567B2 Method of forming a semiconductor memory device and semiconductor memory device 有权
标题翻译：形成半导体存储器件和半导体存储器件的方法
公开(公告)号：US07767567B2
公开(公告)日：2010-08-03
申请号：US11541404
申请日：2006-09-29
申请人： Josef Willer , Franz Hofmann
发明人： Josef Willer , Franz Hofmann
IPC分类号： H01L21/3205
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.
摘要翻译：存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。在为源极线提供的区域中的间隔件之间形成开口。施加牺牲层以填充开口并且随后被图案化。间隙填充有介电材料的平坦化层。去除牺牲层的残余物并施加导电材料以形成源极线。

4. 发明申请

US20090309152A1 Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same 有权
标题翻译：具有接触区域的集成电路及其制造方法
公开(公告)号：US20090309152A1
公开(公告)日：2009-12-17
申请号：US12137388
申请日：2008-06-11
申请人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
发明人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L21/28273 , H01L21/8221 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
摘要翻译：在一个实施例中，提供了具有存储单元布置的集成电路。存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移基材的主要加工表面。

5. 发明申请

US20080096352A1 Method of forming a semiconductor memory device and semiconductor memory device 有权
标题翻译：形成半导体存储器件和半导体存储器件的方法
公开(公告)号：US20080096352A1
公开(公告)日：2008-04-24
申请号：US11541404
申请日：2006-09-29
申请人： Josef Willer , Franz Hofmann
发明人： Josef Willer , Franz Hofmann
IPC分类号： H01L21/336
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.
摘要翻译：存储器单元阵列和多个选择晶体管的栅极堆叠形成在载体上方，栅极堆叠被间隔物隔开。在为源极线提供的区域中的间隔件之间形成开口。施加牺牲层以填充开口并且随后被图案化。间隙填充有介电材料的平坦化层。去除牺牲层的残余物并施加导电材料以形成源极线。

6. 发明申请

US20080035997A1 Fin Field-Effect Transistor and Method for Fabricating a Fin Field-Effect Transistor 审中-公开
标题翻译：翅片场效应晶体管和制造鳍场效应晶体管的方法
公开(公告)号：US20080035997A1
公开(公告)日：2008-02-14
申请号：US11833080
申请日：2007-08-02
申请人： Franz Hofmann , Johannes Kretz , Wolfgang Roesner , Thomas Schulz
发明人： Franz Hofmann , Johannes Kretz , Wolfgang Roesner , Thomas Schulz
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： A fin field-effect transistor has a substrate and a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. The source and drain regions are formed once a gate has been produced.
摘要翻译：翅片场效应晶体管具有在衬底上方的衬底和鳍结构，以及在衬底上方的鳍结构之外的漏极区域和源极区域。鳍结构用作源极区域和漏极区域之间的沟道。源极和漏极区域一旦形成栅极就形成。

7. 发明授权

US07307865B2 Integrated read-only memory, method for operating said read-only memory and corresponding production method 有权
标题翻译：集成只读存储器，用于操作所述只读存储器的方法和相应的制造方法
公开(公告)号：US07307865B2
公开(公告)日：2007-12-11
申请号：US10505320
申请日：2003-02-17
申请人： Franz Hofmann , Richard Johannes Luyken , Till Schlosser
发明人： Franz Hofmann , Richard Johannes Luyken , Till Schlosser
IPC分类号： G11C17/00
CPC分类号： H01L27/28 , H01L27/2436 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/147
摘要： An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer is provided between the drain connections and the electrode, whose electric resistance can be changed under the effect of a configuration voltage or current. The layer may be applied in a backend process.
摘要翻译：具有选择晶体管的集成只读存储器，每个具有漏极连接和用于馈送诸如电压或电流的电信号的电极连接。在漏极连接和电极之间设置一层，其电阻可以在配置电压或电流的作用下改变。该层可以应用在后端进程中。

8. 发明授权

US07157767B2 Semiconductor memory element, semiconductor memory arrangement, method for fabricating a semiconductor memory element and method for operating a semiconductor memory element 有权
标题翻译：半导体存储元件，半导体存储装置，半导体存储元件的制造方法以及半导体存储元件的操作方法
公开(公告)号：US07157767B2
公开(公告)日：2007-01-02
申请号：US10486184
申请日：2002-09-02
申请人： Michael Specht , Franz Hofmann
发明人： Michael Specht , Franz Hofmann
IPC分类号： H01L29/788
CPC分类号： H01L29/513 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/518 , H01L29/66825 , H01L29/7883
摘要： A semiconductor memory element has a substrate, in which a source region and a drain region are formed, a floating gate electrically insulated from the substrate, and a tunnel barrier arrangement, via which charging or discharging of the floating gate can be performed. It is possible to alter the conductivity of a channel between source and drain regions by charging or discharging the floating gate. A source line is electrically conductively connected to the source region and controls the charge transmission of the tunnel barrier arrangement.
摘要翻译：半导体存储元件具有形成源极区域和漏极区域的基板，与基板电绝缘的浮动栅极以及可以进行浮置栅极的充电或放电的隧道势垒装置。通过对浮动栅极进行充电或放电，可以改变源区和漏区之间的沟道的导电性。源极线导电地连接到源极区域并控制隧道势垒装置的电荷传输。

9. 发明授权

US07154138B2 Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for producing a transistor-arrangement 失效
标题翻译：晶体管布置，用于操作晶体管布置作为数据存储元件的方法和用于产生晶体管布置的方法
公开(公告)号：US07154138B2
公开(公告)日：2006-12-26
申请号：US10481278
申请日：2002-06-20
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L27/108 , H01L29/76 , H01L29/788 , H01L29/94
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11553 , H01L29/66833 , H01L29/7923
摘要： The invention relates to a transistor arrangement having a substrate and a vertical transistor comprising: a first electrode region, a second electrode region arranged essentially above the latter, and, in between, a channel region, and also a gate region beside the channel region and, in between, an electrically insulating layer sequence, wherein two mutually spatially separate sections of the electrically insulating layer sequence in each case serve for the storage of charge carriers.
摘要翻译：本发明涉及具有衬底和垂直晶体管的晶体管装置，其包括：第一电极区域，基本上在其上方布置的第二电极区域，以及沟道区域之间以及沟道区域旁边的栅极区域，以及之间，电绝缘层序列，其中电绝缘层序列的两个相互空间分离的部分在每种情况下用于存储电荷载体。

10. 发明申请

US20060022248A1 Electronic data memory device for a high read current 审中-公开
标题翻译：用于高读取电流的电子数据存储器件
公开(公告)号：US20060022248A1
公开(公告)日：2006-02-02
申请号：US11167386
申请日：2005-06-27
申请人： Bjorn Fischer , Franz Hofmann , Richard Luyken , Andreas Spitzer
发明人： Bjorn Fischer , Franz Hofmann , Richard Luyken , Andreas Spitzer
IPC分类号： H01L27/108
CPC分类号： H01L27/10873 , H01L29/7851
摘要： Electronic data memory device for a high read current The invention provides a memory device arranged on a substrate (401) and having at least one memory cell (100) The memory cell comprises a storage capacitor (200) for storing an electrical charge and a selection transistor (300) for selecting the memory cell (100). The selection transistor comprises a first conduction electrode (301), a second conduction electrode (302) and a control electrode (303) , the control electrode (303) being provided by a gate unit (400) having a fin (405) projecting from the substrate (401), which fin is surrounded by a gate oxide layer (406) and a gate electrode layer (403) in such a way that first and second gate elements (408a, 408b) are provided at opposite lateral areas of the fin (405), a third gate element (408c) being provided at an area of the fin (405) that is parallel to the surface of the substrate (401).
摘要翻译：用于高读取电流的电子数据存储器件本发明提供一种布置在衬底（401）上并具有至少一个存储单元（100）的存储器件。存储单元包括用于存储电荷的存储电容器（200）晶体管（300），用于选择存储单元（100）。选择晶体管包括第一导电电极（301），第二导电电极（302）和控制电极（303），控制电极（303）由栅极单元（400）提供，栅极单元（400）具有从基板（401），其被栅极氧化物层（406）和栅极电极层（403）包围，使得第一和第二栅极元件（408a，408b）设置在第一和第二栅极元件（408a，408b）的相对侧向区域所述翅片（405），第三栅极元件（408c）设置在所述鳍状物（405）的与所述基板（401）的表面平行的区域。

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