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1. 发明申请

US20170373928A1 COMPUTER-READABLE RECORDING MEDIUM, INFORMATION PROCESSING APPARATUS, AND VM SWITCHING METHOD 审中-公开
公开(公告)号：US20170373928A1
公开(公告)日：2017-12-28
申请号：US15604710
申请日：2017-05-25
申请人： FUJITSU LIMITED
发明人： Yusuke UJIIE , Motoyuki Tanisho , Tetsuo EHARA
IPC分类号： H04L12/24 , H04L12/26 , H04L12/931
CPC分类号： H04L41/0668 , H04L43/04 , H04L43/0829 , H04L49/70
摘要： A server detects an abnormality of a VM being a transfer destination of a packet; rewrites, when the VM is switched, a first relationship between a transfer destination MAC address and a port number of the VM before switching to a first relationship between the MAC address and a port number of the switched VM; decides, from the port number being matched based on the rewritten first relationship and a second relationship among a port number of the switched VM, a transfer destination MAC address, and a transfer destination IP address, the transfer destination MAC address and the transfer destination IP address of the switched VM; rewrites the transfer destination MAC address and the transfer destination IP address included in the header of the packet received from a network to the decided MAC address and the IP address; and transfers the rewritten packet to the switched VM.

2. 发明申请

US20150356724A1 INFORMATION PROCESSING APPARATUS, METHOD OF OUTPUTTING CIRCUIT IMAGE, AND STORAGE MEDIUM STORING CIRCUIT IMAGE OUTPUT PROGRAM 有权
标题翻译：信息处理装置，输出电路图像的方法和存储介质存储电路图像输出程序
公开(公告)号：US20150356724A1
公开(公告)日：2015-12-10
申请号：US14725294
申请日：2015-05-29
申请人： FUJITSU LIMITED
发明人： SHUICHIRO YAMADA , Motoyuki Tanisho
IPC分类号： G06T7/00 , G06F17/50
CPC分类号： G06F17/505 , G06F17/30554 , G06F17/5045 , G06F17/5054 , G06F17/5068 , G06F17/5072 , G06F2217/74
摘要： An information processing apparatus includes a processor and a memory configured to store therein correspondence information defining an association relationship between position of the connection point of circuits and information of wiring which has one end located at the position of the connection point. The processor is configured to identify a first circuit from a group of multiple images representing an overall circuit, acquire, based on the correspondence information, information of a first position of a connection point of a second circuit at which the identified first circuit is coupled and information of a first wiring which one end is located at the first position, extract, from the second image, a partial image that includes images of the first wiring and the connection point at the first position based on the acquired information of the first position and the first wiring, and output the extracted partial image.
摘要翻译：一种信息处理装置，包括处理器和存储器，其被配置为在其中存储定义电路的连接点的位置与一端位于连接点的位置的布线的信息之间的关联关系的对应信息。处理器被配置为从表示总体电路的一组多个图像中识别第一电路，基于对应信息，获取所识别的第一电路耦合的第二电路的连接点的第一位置的信息，以及一端位于第一位置的第一布线的信息，基于所获取的第一位置的信息，从第二图像中提取包括第一布线和第一位置的连接点的图像的部分图像，以及第一布线，并输出提取的部分图像。

3. 发明申请

US20170012855A1 NETWORK PROCESSOR, COMMUNICATION DEVICE, PACKET TRANSFER METHOD, AND COMPUTER-READABLE RECORDING MEDIUM 有权
标题翻译：网络处理器，通信设备，分组传输方法和计算机可读记录介质
公开(公告)号：US20170012855A1
公开(公告)日：2017-01-12
申请号：US15155182
申请日：2016-05-16
申请人： FUJITSU LIMITED
发明人： Yasutaka Kanayama , Motoyuki Tanisho
IPC分类号： H04L12/755 , H04L12/861 , H04L12/24 , H04L12/741
CPC分类号： H04L41/0813 , H04L41/085
摘要： A managing unit adds update information to an entry to be updated of a table updated prior to a change of a network configuration, and deletes the update information when the update of the table caused by the change of the network configuration is completed. A packet processing unit executes a plurality of pipeline processes using the table sequentially, and suspends executing the pipeline processes when the update information is added to any entry of the table. A reprocessing control unit stores an input packet in a reprocessing queue when the pipeline processes executed by the packet processing unit is suspended, and transfers the packet stored in the reprocessing queue to the input queue when update of the table to which the update information is added is all completed.
摘要翻译：管理单元将更新信息添加到在更改网络配置之前更新的表的要更新的条目，并且当由网络配置的改变引起的表的更新完成时，删除更新信息。分组处理单元依次使用表执行多个流水线处理，并且当更新信息被添加到表的任何条目时，暂停执行流水线处理。当由分组处理单元执行的流水线处理被暂停时，再处理控制单元将输入分组存储在再处理队列中，并且当更新添加了更新信息的表时，将存储在再处理队列中的分组传送到输入队列全部完成

4. 发明申请

US20170005939A1 CONTROL METHOD AND NETWORK DEVICE 审中-公开
标题翻译：控制方法和网络设备
公开(公告)号：US20170005939A1
公开(公告)日：2017-01-05
申请号：US15187969
申请日：2016-06-21
申请人： FUJITSU LIMITED
发明人： Motoyuki Tanisho , Tetsuo Ehara , Norihide Kubota , Shigeru Tsukada , Yuji Tanaka
IPC分类号： H04L12/819 , H04L12/841 , H04L12/813
CPC分类号： H04L47/215 , H04L47/20 , H04L47/22 , H04L47/28
摘要： A control method performed by a network device includes replenishing a token to a token bucket and updating a timestamp indicating an execution time point of a meter operation when a user packet is received from another device, generating a dummy packet different from the user packet for every certain time period, in response to the dummy packet, replenishing the token to the token bucket, updating the timestamp, and discarding the dummy packet, controlling traffic in accordance with the token within the token bucket.
摘要翻译：由网络设备执行的控制方法包括向令牌桶补充令牌，并且当从另一设备接收到用户分组时更新指示仪表操作的执行时间点的时间戳，生成与用户分组不同的虚拟分组特定时间段，响应于虚拟分组，将令牌补充到令牌桶，更新时间戳，并丢弃虚拟分组，根据令牌桶内的令牌来控制流量。

5. 发明授权

US10015076B2 Network processor, communication device, packet transfer method, and computer-readable recording medium 有权
公开(公告)号：US10015076B2
公开(公告)日：2018-07-03
申请号：US15155182
申请日：2016-05-16
申请人： FUJITSU LIMITED
发明人： Yasutaka Kanayama , Motoyuki Tanisho
IPC分类号： H04L12/28 , H04L12/755 , H04L12/741 , H04L12/861 , H04L12/24
CPC分类号： H04L41/0813 , H04L41/085
摘要： A managing unit adds update information to an entry to be updated of a table updated prior to a change of a network configuration, and deletes the update information when the update of the table caused by the change of the network configuration is completed. A packet processing unit executes a plurality of pipeline processes using the table sequentially, and suspends executing the pipeline processes when the update information is added to any entry of the table. A reprocessing control unit stores an input packet in a reprocessing queue when the pipeline processes executed by the packet processing unit is suspended, and transfers the packet stored in the reprocessing queue to the input queue when update of the table to which the update information is added is all completed.

6. 发明授权

US11088960B2 Information processing apparatus and verification system 有权
公开(公告)号：US11088960B2
公开(公告)日：2021-08-10
申请号：US16405351
申请日：2019-05-07
申请人： FUJITSU LIMITED
发明人： Motoyuki Tanisho
IPC分类号： H04L12/863 , H04L12/865 , H04L12/911 , H04L12/851
摘要： An information processing apparatus includes a processor that obtains a flow table from a switch apparatus that processes packets by using the flow table. The processor creates, for each flow registered with the flow table, a verification packet based on identification information that identifies each flow. The processor determines a number of verification packets based on a count value that represents a number of actual packets that have arrived at the switch apparatus. The processor generates the number of verification packets for each flow by copying the verification packet created for each flow. The processor determines transmission order of the generated verification packets based on the count value for each flow and time information that represents a time when a final actual packet of each flow has arrived at the switch apparatus.

7. 发明申请

US20190356605A1 INFORMATION PROCESSING APPARATUS AND VERIFICATION SYSTEM 审中-公开
公开(公告)号：US20190356605A1
公开(公告)日：2019-11-21
申请号：US16405351
申请日：2019-05-07
申请人： FUJITSU LIMITED
发明人： Motoyuki Tanisho
IPC分类号： H04L12/863 , H04L12/851 , H04L12/911 , H04L12/865
摘要： An information processing apparatus includes a processor that obtains a flow table from a switch apparatus that processes packets by using the flow table. The processor creates, for each flow registered with the flow table, a verification packet based on identification information that identifies each flow. The processor determines a number of verification packets based on a count value that represents a number of actual packets that have arrived at the switch apparatus. The processor generates the number of verification packets for each flow by copying the verification packet created for each flow. The processor determines transmission order of the generated verification packets based on the count value for each flow and time information that represents a time when a final actual packet of each flow has arrived at the switch apparatus.

8. 发明授权

US09626469B2 Information processing apparatus, method of outputting circuit image, and storage medium storing circuit image output program 有权
公开(公告)号：US09626469B2
公开(公告)日：2017-04-18
申请号：US14725294
申请日：2015-05-29
申请人： FUJITSU LIMITED
发明人： Shuichiro Yamada , Motoyuki Tanisho
IPC分类号： G06F17/50 , G06F17/30
CPC分类号： G06F17/505 , G06F17/30554 , G06F17/5045 , G06F17/5054 , G06F17/5068 , G06F17/5072 , G06F2217/74
摘要： An information processing apparatus includes a processor and a memory configured to store therein correspondence information defining an association relationship between position of the connection point of circuits and information of wiring which has one end located at the position of the connection point. The processor is configured to identify a first circuit from a group of multiple images representing an overall circuit, acquire, based on the correspondence information, information of a first position of a connection point of a second circuit at which the identified first circuit is coupled and information of a first wiring which one end is located at the first position, extract, from the second image, a partial image that includes images of the first wiring and the connection point at the first position based on the acquired information of the first position and the first wiring, and output the extracted partial image.

9. 发明授权

US08813002B2 Circuit board design support program, design support method, and design support apparatus 有权
标题翻译：电路板设计支持方案，设计支持方法和设计支持设备
公开(公告)号：US08813002B2
公开(公告)日：2014-08-19
申请号：US14013079
申请日：2013-08-29
申请人： Fujitsu Limited
发明人： Motoyuki Tanisho
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F11/366 , G06F17/5045
摘要： The embodiment is a non-transitory computer readable storage medium storing a design support program which causes a computer to generate design data for a circuit board in which elements are placed. The program causes the computer to perform: storing, in response to an operation input, operation information in an operation storage section; storing a function of a program executed based on the operation input in a function history storage section; upon detection of an operation of a command causing the computer to execute a predetermined function for generating the design data, acquiring a selected element and storing the selected element in an element information storage section; and detecting an abnormal end of the predetermined function to output the function of the program in the function history storage section, the operation information in the operation information storage section, and the element in the element information storage section to a log file.
摘要翻译：该实施例是存储设计支持程序的非暂时计算机可读存储介质，其使得计算机生成其中放置元件的电路板的设计数据。该程序使计算机执行以下操作：响应于操作输入将操作信息存储在操作存储部分中; 将基于所述操作输入执行的程序的功能存储在功能历史存储部中; 在检测到使计算机执行用于生成设计数据的预定功能的命令的操作时，获取所选择的元素并将所选择的元素存储在元素信息存储部分中; 并且检测预定功能的异常结束，将功能历史存储部中的程序的功能，操作信息存储部中的操作信息和元素信息存储部中的元素输出到日志文件。

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