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1. 发明授权

US09349635B2 Integrated circuits and methods of forming the same with multi-level electrical connection 有权
标题翻译：集成电路和与多级电气连接形成的方法
公开(公告)号：US09349635B2
公开(公告)日：2016-05-24
申请号：US13770464
申请日：2013-02-19
申请人： GLOBALFOUNDRIES, Inc.
发明人： San Leong Liew , Huang Liu
IPC分类号： H01L21/768 , H01L23/532 , H01L23/522
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/5228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods of forming integrated circuits are provided. A method of forming an integrated circuit includes providing a substrate that includes an electrical contact disposed therein. A first dielectric layer is formed over the substrate and electrical contact. A metal-containing layer is patterned over the first dielectric layer, with at least a first portion of the patterned metal-containing layer disposed over the first dielectric layer. The patterned metal-containing layer is absent in regions of the first dielectric layer over the electrical contact. A second dielectric layer is formed over the patterned metal-containing layer. A first via is etched in the first dielectric layer and the second dielectric layer over the electrical contact, and a second via is etched in the second dielectric layer over the patterned metal-containing layer. The first via and the second via are filled with an electrically-conductive material.
摘要翻译：提供了形成集成电路的集成电路和方法。形成集成电路的方法包括提供包括设置在其中的电接触的基板。第一电介质层形成在衬底上并进行电接触。在第一介电层上图案化含金属层，其中图案化的含金属层的至少第一部分设置在第一介电层上。在电触点上的第一介电层的区域中不存在图案化的含金属层。在图案化的含金属层上形成第二介电层。在第一电介质层和第二电介质层上蚀刻第一通孔，并且在图案化的含金属层上的第二介电层中蚀刻第二通孔。第一通孔和第二通孔被填充有导电材料。

2. 发明申请

US20140232010A1 INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH MULTI-LEVEL ELECTRICAL CONNECTION 有权
标题翻译：集成电路及其与多级电气连接的形成方法
公开(公告)号：US20140232010A1
公开(公告)日：2014-08-21
申请号：US13770464
申请日：2013-02-19
申请人： GLOBALFOUNDRIES, INC.
发明人： San Leong Liew , Huang Liu
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/5228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods of forming integrated circuits are provided. A method of forming an integrated circuit includes providing a substrate that includes an electrical contact disposed therein. A first dielectric layer is formed over the substrate and electrical contact. A metal-containing layer is patterned over the first dielectric layer, with at least a first portion of the patterned metal-containing layer disposed over the first dielectric layer. The patterned metal-containing layer is absent in regions of the first dielectric layer over the electrical contact. A second dielectric layer is formed over the patterned metal-containing layer. A first via is etched in the first dielectric layer and the second dielectric layer over the electrical contact, and a second via is etched in the second dielectric layer over the patterned metal-containing layer. The first via and the second via are filled with an electrically-conductive material.
摘要翻译：提供了形成集成电路的集成电路和方法。形成集成电路的方法包括提供包括设置在其中的电接触的基板。第一电介质层形成在衬底上并进行电接触。在第一介电层上图案化含金属层，其中图案化的含金属层的至少第一部分设置在第一介电层上。在电触点上的第一介电层的区域中不存在图案化的含金属层。在图案化的含金属层上形成第二介电层。在第一电介质层和第二电介质层上蚀刻第一通孔，并且在图案化的含金属层上的第二介电层中蚀刻第二通孔。第一通孔和第二通孔被填充有导电材料。

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