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1. 发明授权

US10049570B2 Controlling right-of-way for priority vehicles 有权
公开(公告)号：US10049570B2
公开(公告)日：2018-08-14
申请号：US14918776
申请日：2015-10-21
申请人： GLOBALFOUNDRIES INC.
发明人： Eric A. Foreman , Sudeep Mandal
IPC分类号： G08G1/0965 , G01C21/34 , G08G1/087 , G01C21/36
摘要： Various embodiments include approaches for analyzing a set of travel pathways for a priority vehicle. In some cases, an approach includes: obtaining data indicating a location of the priority vehicle and a location of a destination for the priority vehicle; ranking each of a set of paths between the location of the priority vehicle and the location of the destination based upon a travel time for the priority vehicle along the set of paths; and sending instructions to vehicles on a highest-ranked path in the set of paths to initiate providing a right-of-way to the priority vehicle, wherein vehicles closer to the destination along the highest-ranked path are instructed to change a corresponding position prior to vehicles farther from the destination along the highest-ranked path.

2. 发明授权

US10043962B2 Thermoelectric cooling using through-silicon vias 有权
公开(公告)号：US10043962B2
公开(公告)日：2018-08-07
申请号：US15147595
申请日：2016-05-05
申请人： GLOBALFOUNDRIES INC.
发明人： Sudeep Mandal , Richard S. Graf
IPC分类号： H01L35/30 , H01L35/32 , H01L35/10 , H01L23/38 , H01L35/34
摘要： Structures that include thermoelectric couples and methods for fabricating such structures. A device level and a back-end-of-line (BEOL) interconnect structure are fabricated at a front side of a substrate. A thermoelectric couple is formed that is coupled with the substrate. The thermoelectric couple includes a first through-silicon via extending through the device level and the substrate to a back side of the substrate, a second through-silicon via extending through the device level and the substrate to the back side of the substrate, an n-type thermoelectric pillar coupled with the first through-silicon via, and a p-type thermoelectric pillar coupled with the second through-silicon via. The BEOL interconnect structure includes a wire that couples the first through-silicon via in series with the second through-silicon via.

3. 发明授权

US09892999B2 Producing wafer level packaging using leadframe strip and related device 有权
公开(公告)号：US09892999B2
公开(公告)日：2018-02-13
申请号：US15175290
申请日：2016-06-07
申请人： GLOBALFOUNDRIES Inc.
发明人： Richard S. Graf , Sudeep Mandal , Kibby Horsford
IPC分类号： H01L21/78 , H01L21/56 , H01L23/28 , H01L23/495 , H01L21/48 , H01L23/00 , H01L25/065
CPC分类号： H01L23/49575 , H01L21/486 , H01L21/561 , H01L21/565 , H01L23/3128 , H01L23/49541 , H01L23/49579 , H01L23/49586 , H01L23/49816 , H01L23/49861 , H01L23/49866 , H01L23/5389 , H01L24/11 , H01L24/14 , H01L24/19 , H01L24/96 , H01L25/0652 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/24175 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/1094 , H01L2924/15311
摘要： A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.

4. 发明授权

US09871020B1 Through silicon via sharing in a 3D integrated circuit 有权
公开(公告)号：US09871020B1
公开(公告)日：2018-01-16
申请号：US15210403
申请日：2016-07-14
申请人： GLOBALFOUNDRIES INC.
发明人： Sebastian T. Ventrone , Sudeep Mandal
IPC分类号： G11C15/00 , G11C15/04 , G11C15/06 , H01L25/065
CPC分类号： H01L25/0657 , G11C15/04 , G11C15/06 , H01L2225/0652 , H01L2225/06548 , H01L2225/06558 , H01L2225/06572
摘要： The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies.

5. 发明申请

US20160117433A1 INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION 审中-公开
标题翻译：集成电路时序可变性降低
公开(公告)号：US20160117433A1
公开(公告)日：2016-04-28
申请号：US14525320
申请日：2014-10-28
申请人： GLOBALFOUNDRIES INC.
发明人： Eric A. Foreman , Chaitanya Kompalli , Sudeep Mandal , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： As disclosed herein, a method, executed by a computer, for integrated circuit timing variability reduction includes loading a netlist that corresponds to a chip design, where the chip design includes one or more circuits and a plurality of post-fill features, traversing a portion of the netlist corresponding to a circuit, determining a post-fill environment for the circuit from a plurality of post-fill features, and modeling a timing variance for the circuit based on the post-fill environment. The method may also include changing one or more post-fill features to achieve a targeted delay. The method may include generating a report of circuit timing and timing variances. One or more circuits can be concurrently traversed. The timing variance can be modeled with the use of a scaling factor for a standard timing variance. A computer system and computer program product corresponding to the method are also disclosed herein.
摘要翻译：如本文所公开的，由计算机执行的用于集成电路定时可变性降低的方法包括加载对应于芯片设计的网表，其中芯片设计包括一个或多个电路和多个后填充特征，遍历部分所述网表对应于电路，从多个后填充特征确定所述电路的填充后环境，以及基于所述填充后环境对所述电路的定时方差进行建模。该方法还可以包括改变一个或多个后填充特征以实现目标延迟。该方法可以包括生成电路定时和定时方差的报告。可以同时遍历一个或多个电路。定时方差可以用标准时间方差的缩放因子来建模。本文还公开了与该方法对应的计算机系统和计算机程序产品。

6. 发明申请

US20180052388A1 ADJUSTING OF PATTERNS IN DESIGN LAYOUT FOR OPTICAL PROXIMITY CORRECTION 有权
公开(公告)号：US20180052388A1
公开(公告)日：2018-02-22
申请号：US15239072
申请日：2016-08-17
申请人： GLOBALFOUNDRIES INC.
发明人： Sudeep Mandal , Arun S. Mampazhy
IPC分类号： G03F1/36 , G06F17/50
CPC分类号： G03F1/36 , G06F17/5081
摘要： Embodiments of the present disclosure include methods, program products, and systems for adjusting an integrated circuit (IC) layout for optical proximity correction (OPC). Methods according to the disclosure can include: defining a target region of the IC design layout, the target region having a plurality of patterns including a first pattern positioned adjacent to a second pattern, wherein an OPC modeling rule of the IC design layout prohibits the first pattern from being adjusted, and wherein the second pattern does not reduce a printability metric of the first pattern; adjusting the design of the second pattern to reduce at least one printing error in the first pattern, wherein a functionality of the second pattern in the IC design layout is unchanged after the adjusting; and implementing OPC on the IC design layout including the target region with the adjusted second pattern therein.

7. 发明授权

US09496234B1 Wafer-level chip-scale package structure utilizing conductive polymer 有权
标题翻译：使用导电聚合物的晶圆级芯片级封装结构
公开(公告)号：US09496234B1
公开(公告)日：2016-11-15
申请号：US14741802
申请日：2015-06-17
申请人： GLOBALFOUNDRIES INC.
发明人： Richard S. Graf , Kibby B. Horsford , Sudeep Mandal
IPC分类号： H01L23/48 , H01L23/00
CPC分类号： H01L24/13 , H01L23/3114 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/94 , H01L2224/0345 , H01L2224/0347 , H01L2224/0361 , H01L2224/03828 , H01L2224/03912 , H01L2224/0401 , H01L2224/05073 , H01L2224/05082 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/1132 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/119 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13171 , H01L2224/1329 , H01L2224/13339 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/1339 , H01L2224/13444 , H01L2224/13455 , H01L2224/94 , H01L2924/00015 , H01L2924/381 , H01L2224/11 , H01L2924/014 , H01L2924/00014 , H01L2924/01029 , H01L2924/01023 , H01L2924/01074 , H01L2224/11334 , H01L2224/023 , H01L2224/03
摘要： An integrated conductive polymer-solder ball structure is provided. The integrated conductive polymer-solder ball structure comprises a sputter seed layer applied to a wafer structure, one or more conductive polymer pad structures applied to the sputtered seed layer at locations on the wafer structure where one or more solder ball structures will be formed, an electroplating layer applied to portions of the one or more conductive polymer pad structures where a photoresist layer has been exposed, and a solder ball formed on each of the electroplating layers thereby forming the one or more solder ball structures.
摘要翻译：提供了一种集成的导电聚合物 - 焊球结构。集成导电聚合物 - 焊球结构包括施加到晶片结构的溅射籽晶层，在晶片结构上将形成一个或多个焊球结构的位置处施加到溅射种子层的一个或多个导电聚合物垫结构，电镀层施加到已经暴露光致抗蚀剂层的一个或多个导电聚合物垫结构的部分，以及形成在每个电镀层上的焊球，从而形成一个或多个焊球结构。

8. 发明授权

US10304763B2 Producing wafer level packaging using leadframe strip and related device 有权
公开(公告)号：US10304763B2
公开(公告)日：2019-05-28
申请号：US15858673
申请日：2017-12-29
申请人： GLOBALFOUNDRIES Inc.
发明人： Richard S. Graf , Sudeep Mandal , Kibby Horsford
IPC分类号： H01L23/495 , H01L21/48 , H01L21/56 , H01L23/00 , H01L25/065 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/10
摘要： A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.

9. 发明申请

US20180082007A1 PERFORMANCE MATCHING IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) USING BACK-BIAS COMPENSATION 有权
公开(公告)号：US20180082007A1
公开(公告)日：2018-03-22
申请号：US15270598
申请日：2016-09-20
申请人： GLOBALFOUNDRIES INC.
发明人： Sudeep Mandal , Jeanne P. Bickford
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Various embodiments include approaches for designing three-dimensional (3D) integrated circuits (ICs). In one embodiment, a system is configured to: read an electronic chip identification (ECID) for a plurality of dies formed from distinct wafer lots, the ECID indicating a process performance parameter for each distinct wafer lot; create a reference table mapping a back-bias voltage to be applied to each die to the process performance parameter for each distinct wafer lot; determine performance requirements of a customer design for the 3D IC structure; assemble the design of the 3D IC structure including a set of dies selected from at least two of the distinct wafer lots; and assign a back bias voltage to each die based upon the performance requirements of the customer design and the reference table.

10. 发明申请

US20170271285A1 INTEGRATED CIRCUIT PACKAGE USING POLYMER-SOLDER BALL STRUCTURES AND FORMING METHODS 审中-公开
公开(公告)号：US20170271285A1
公开(公告)日：2017-09-21
申请号：US15072655
申请日：2016-03-17
申请人： GLOBALFOUNDRIES INC.
发明人： Richard S. Graf , Kibby B. Horsford , Sudeep Mandal
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0332 , H01L2224/03464 , H01L2224/0362 , H01L2224/03828 , H01L2224/0401 , H01L2224/05008 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/0519 , H01L2224/0529 , H01L2224/05339 , H01L2224/05344 , H01L2224/05347 , H01L2224/05355 , H01L2224/0539 , H01L2224/05444 , H01L2224/05455 , H01L2224/05564 , H01L2224/05573 , H01L2224/05655 , H01L2224/11334 , H01L2224/11849 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1319 , H01L2224/94 , H01L2224/03 , H01L2224/11 , H01L2924/013 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/01005 , H01L2924/01015
摘要： A conductive polymer-solder ball structure is provided. The conductive polymer-solder ball structure includes a wafer having at least one metal pad providing an electrical conductive path to a substrate layer, a conductive polymer pad located directly on the wafer over the at least one metal pad, an electrolessly plated layer located on a surface of the conductive polymer pad, and a solder ball located on a surface of the electrolessly plated layer.

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