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1. 发明授权

US09564440B2 Spacer chamfering gate stack scheme 有权
标题翻译：间隔倒角门堆叠方案
公开(公告)号：US09564440B2
公开(公告)日：2017-02-07
申请号：US15232246
申请日：2016-08-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES INC.
发明人： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC分类号： H01L27/092 , H01L29/66 , H01L29/49 , H01L29/423 , H01L21/8238
CPC分类号： H01L29/512 , H01L21/02532 , H01L21/0262 , H01L21/28088 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.
摘要翻译：一种形成用于半导体器件的栅极结构的方法，包括在存在于鳍状结构上的置换栅极结构的侧壁上形成第一间隔物，其中第一间隔物的上表面偏离替换栅极结构的上表面并且在所述第一间隔物和所述替换栅极结构的所述暴露表面上形成至少第二间隔物。该方法还可以包括用相邻的第一间隔件之间的第一空间中具有第一宽度部分的功能栅极结构代替替换栅极结构，以及在相邻的第二间隔物之间的第二空间中具有第二宽度的第二宽度部分，其中第二宽度大于第一宽度。

2. 发明授权

US09236557B2 Magnetic tunnel junction between metal layers of a semiconductor device 有权
标题翻译：半导体器件的金属层之间的磁隧道结
公开(公告)号：US09236557B2
公开(公告)日：2016-01-12
申请号：US14156210
申请日：2014-01-15
申请人： GLOBALFOUNDRIES Inc.
发明人： Xunyuan Zhang , Ruilong Xie , Xiuyu Cai , Hyun-Jin Cho
IPC分类号： H01L21/00 , H01L43/02 , H01L43/12
CPC分类号： H01L43/02 , H01L43/12
摘要： Embodiments herein provide a magnetic tunnel junction (MTJ) formed between metal layers of a semiconductor device. Specifically, provided is an approach for forming the semiconductor device using only one or two masks, the approach comprising: forming a first metal layer in a dielectric layer of the semiconductor device, forming a bottom electrode layer over the first metal layer, forming a MTJ over the bottom electrode layer, forming a top electrode layer over the MTJ, patterning the top electrode layer and the MTJ with a first mask, and forming a second metal layer over the top electrode layer. Optionally, the bottom electrode layer may be patterned using a second mask. Furthermore, in another embodiment, an insulator layer (e.g., manganese) is formed atop the dielectric layer, wherein a top surface of the first metal layer remains exposed following formation of the insulator layer such that the bottom electrode layer contacts the top surface of the first metal layer. By forming the MTJ between the metal layers using only one or two masks, the overall number of processing steps is reduced.
摘要翻译：本文的实施例提供了形成在半导体器件的金属层之间的磁性隧道结（MTJ）。具体地，提供了仅使用一个或两个掩模形成半导体器件的方法，所述方法包括：在所述半导体器件的电介质层中形成第一金属层，在所述第一金属层上形成底部电极层，形成MTJ 在所述底部电极层上方，在所述MTJ上形成顶部电极层，用第一掩模图案化所述顶部电极层和所述MTJ，以及在所述顶部电极层上方形成第二金属层。可选地，可以使用第二掩模对底部电极层进行图案化。此外，在另一个实施例中，绝缘体层（例如，锰）形成在电介质层的顶部，其中第一金属层的顶表面在形成绝缘体层之后保持暴露，使得底部电极层接触绝缘层的顶表面第一金属层。通过仅使用一个或两个掩模在金属层之间形成MTJ，减少了处理步骤的总数。

3. 发明申请

US20150200353A1 MAGNETIC TUNNEL JUNCTION BETWEEN METAL LAYERS OF A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件金属层之间的磁性隧道结
公开(公告)号：US20150200353A1
公开(公告)日：2015-07-16
申请号：US14156210
申请日：2014-01-15
申请人： GLOBALFOUNDRIES Inc.
发明人： Xunyuan Zhang , Ruilong Xie , Xiuyu Cai , Hyun-Jin Cho
IPC分类号： H01L43/02 , H01L43/12
CPC分类号： H01L43/02 , H01L43/12
摘要： Embodiments herein provide a magnetic tunnel junction (MTJ) formed between metal layers of a semiconductor device. Specifically, provided is an approach for forming the semiconductor device using only one or two masks, the approach comprising: forming a first metal layer in a dielectric layer of the semiconductor device, forming a bottom electrode layer over the first metal layer, forming a MTJ over the bottom electrode layer, forming a top electrode layer over the MTJ, patterning the top electrode layer and the MTJ with a first mask, and forming a second metal layer over the top electrode layer. Optionally, the bottom electrode layer may be patterned using a second mask. Furthermore, in another embodiment, an insulator layer (e.g., manganese) is formed atop the dielectric layer, wherein a top surface of the first metal layer remains exposed following formation of the insulator layer such that the bottom electrode layer contacts the top surface of the first metal layer. By forming the MJT between the metal layers using only one or two masks, the overall number of processing steps is reduced.
摘要翻译：本文的实施例提供了形成在半导体器件的金属层之间的磁性隧道结（MTJ）。具体地，提供了仅使用一个或两个掩模形成半导体器件的方法，所述方法包括：在所述半导体器件的电介质层中形成第一金属层，在所述第一金属层上形成底电极层，形成MTJ 在所述底部电极层上方，在所述MTJ上形成顶部电极层，用第一掩模图案化所述顶部电极层和所述MTJ，以及在所述顶部电极层上方形成第二金属层。可选地，可以使用第二掩模对底部电极层进行图案化。此外，在另一个实施例中，绝缘体层（例如，锰）形成在电介质层的顶部，其中第一金属层的顶表面在形成绝缘体层之后保持暴露，使得底部电极层接触绝缘层的顶表面第一金属层。通过仅使用一个或两个掩模在金属层之间形成MJT，减少了处理步骤的总数。

4. 发明申请

US20150079773A1 CONFORMAL DOPING FOR FINFET DEVICES 有权
标题翻译： FINFET器件的一致性掺杂
公开(公告)号：US20150079773A1
公开(公告)日：2015-03-19
申请号：US14028517
申请日：2013-09-16
申请人： GLOBALFOUNDRIES Inc. , International Business Machines Corporation
发明人： Veeraraghavan S. Basker , Nathaniel Berliner , Hyun-Jin Cho , Johnathan Faltermeler , Kam-Leung Lee , Tenko Yamashita
IPC分类号： H01L21/18
CPC分类号： H01L21/18 , H01L21/2236 , H01L21/2251 , H01L21/845 , H01L29/66803
摘要： A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFETfins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.
摘要翻译：在包括NFET鳍片和PFET鳍片的半导体衬底上的FinFET器件的共形掺杂工艺。在第一示例性实施例中，N型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。将半导体衬底退火以将N型掺杂剂从N型掺杂剂组合物驱动到NFET鳍中。 P型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。将半导体衬底退火以将P型掺杂剂从P型掺杂剂组合物驱动到PFET鳍中。在第二示例性实施例中，可以用第一掺杂剂组合物覆盖NFET烯烃和PFET鳍中的一个，然后第二掺杂剂组合物可以覆盖NFET鳍和PFET鳍，然后进行退火以在两种掺杂剂中驱动。

5. 发明授权

US09780185B2 Spacer chamfering gate stack scheme 有权
公开(公告)号：US09780185B2
公开(公告)日：2017-10-03
申请号：US15232300
申请日：2016-08-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES INC.
发明人： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC分类号： H01L29/51 , H01L27/092 , H01L29/78 , H01L29/66 , H01L29/49 , H01L29/423 , H01L21/8238 , H01L21/02 , H01L21/28 , H01L27/12
CPC分类号： H01L29/512 , H01L21/02532 , H01L21/0262 , H01L21/28088 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

6. 发明申请

US20160365348A1 SPACER CHAMFERING GATE STACK SCHEME 有权
公开(公告)号：US20160365348A1
公开(公告)日：2016-12-15
申请号：US15232246
申请日：2016-08-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES INC.
发明人： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/423 , H01L29/66 , H01L29/49
CPC分类号： H01L29/512 , H01L21/02532 , H01L21/0262 , H01L21/28088 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

7. 发明申请

US20160365290A1 SPACER CHAMFERING GATE STACK SCHEME 有权
公开(公告)号：US20160365290A1
公开(公告)日：2016-12-15
申请号：US15232300
申请日：2016-08-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES INC.
发明人： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC分类号： H01L21/8238 , H01L21/28 , H01L29/66 , H01L27/092 , H01L29/49
CPC分类号： H01L29/512 , H01L21/02532 , H01L21/0262 , H01L21/28088 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/42364 , H01L29/42376 , H01L29/4238 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

8. 发明授权

US09190260B1 Topological method to build self-aligned MTJ without a mask 有权
标题翻译：构建自对准MTJ无掩模的拓扑方法
公开(公告)号：US09190260B1
公开(公告)日：2015-11-17
申请号：US14540504
申请日：2014-11-13
申请人： GLOBALFOUNDRIES Inc.
发明人： Xunyuan Zhang , Ruilong Xie , Xiuyu Cai , Seowoo Nam , Hyun-Jin Cho
IPC分类号： H01L43/12 , H01L21/02 , H01L27/22
CPC分类号： H01L43/08 , G11C11/161 , H01L21/02 , H01L27/222 , H01L27/226 , H01L27/228 , H01L43/02 , H01L43/12
摘要： A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.
摘要翻译：提供了不使用光刻掩模形成自对准MTJ的方法和所得到的器件。实施例包括在金属层上形成第一电极，金属层凹入低k电介质层中; 在第一电极上形成MTJ层; 在MTJ层上形成第二电极; 将所述第二电极，所述MTJ层和所述第一电极的部分去除到所述低k电介质层; 在所述第二电极和所述低k电介质层上形成氮化硅基层; 并将氮化硅基层平坦化到第二电极。

9. 发明授权

US10586855B2 Spacer chamfering gate stack scheme 有权
公开(公告)号：US10586855B2
公开(公告)日：2020-03-10
申请号：US15961264
申请日：2018-04-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES INC.
发明人： Hyun-Jin Cho , Tenko Yamashita , Hui Zang
IPC分类号： H01L29/51 , H01L27/092 , H01L29/78 , H01L29/66 , H01L29/49 , H01L29/423 , H01L21/84 , H01L21/8238 , H01L21/02 , H01L21/28 , H01L27/12
摘要： A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

10. 发明申请

US20190027370A1 SHAPED CAVITY FOR EPITAXIAL SEMICONDUCTOR GROWTH 审中-公开
公开(公告)号：US20190027370A1
公开(公告)日：2019-01-24
申请号：US15653594
申请日：2017-07-19
申请人： GLOBALFOUNDRIES Inc.
发明人： George R. Mulfinger , Hyun-Jin Cho , Anil Kumar , Timothy J. McArdle
IPC分类号： H01L21/306 , H01L29/08 , H01L21/02 , H01L29/06 , H01L29/66
摘要： Methods of forming a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a cavity extending through the semiconductor fin and into a substrate fin underlying the semiconductor fin. After the cavity is formed, the semiconductor fin is etched selective to the substrate fin with a second etching process to widen a portion of the cavity.

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