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1. 发明授权

US09426900B2 Solder void reduction for component attachment to printed circuit boards 有权
标题翻译：用于零件附着到印刷电路板的焊料空隙减少
公开(公告)号：US09426900B2
公开(公告)日：2016-08-23
申请号：US14078777
申请日：2013-11-13
申请人： GLOBALFOUNDRIES Inc.
发明人： Phillip D. Isaacs
IPC分类号： H05K1/02 , H05K3/34
CPC分类号： H05K3/3436 , H05K1/0206 , H05K1/0209 , H05K2201/09063 , H05K2201/09781 , H05K2203/0207 , H05K2203/1178 , Y02P70/613 , Y10T29/49144 , Y10T29/49165
摘要： A method includes fabricating a printed circuit board. The fabricating includes forming at least one conductive layer on top a first dielectric layer. The fabricating includes forming a second dielectric layer on top of the at least one conductive layer. The fabricating includes forming a thermal pad on top of the second dielectric layer. The fabricating includes forming a first through hole through the thermal pad, the second dielectric layer, the at least one conductive layer, and the first dielectric layer. The fabricating includes filling the first through hole with a conductive material to form a plated through hole. The fabricating includes topdrilling the plated through hole to remove a top portion of the conductive material from a top of the plated through hole, wherein a bottom portion of the conductive material remains in the plated through hole after removal of the top portion.
摘要翻译：一种方法包括制造印刷电路板。该制造包括在第一介电层的顶部上形成至少一个导电层。该制造包括在至少一个导电层的顶部上形成第二电介质层。该制造包括在第二介电层的顶部上形成热垫。该制造包括形成通过热垫，第二介电层，至少一个导电层和第一介电层的第一通孔。该制造包括用导电材料填充第一通孔以形成电镀通孔。该制造包括顶部钻孔电镀通孔以从电镀通孔的顶部去除导电材料的顶部，其中在去除顶部部分之后，导电材料的底部部分保留在电镀通孔中。

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