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1. 发明申请

US20200335594A1 SHAPED GATE CAPS IN DIELECTRIC-LINED OPENINGS 审中-公开
公开(公告)号：US20200335594A1
公开(公告)日：2020-10-22
申请号：US16386545
申请日：2019-04-17
申请人： GLOBALFOUNDRIES Inc.
发明人： Hui Zang , Shesh Mani Pandey
IPC分类号： H01L29/423 , H01L21/28 , H01L21/8234 , H01L29/78 , H01L29/06 , H01L21/768 , H01L21/321
摘要： Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.

2. 发明授权

US10672710B2 Interconnect structures with reduced capacitance 审中-公开
公开(公告)号：US10672710B2
公开(公告)日：2020-06-02
申请号：US16000174
申请日：2018-06-05
申请人： GLOBALFOUNDRIES INC.
发明人： Sunil Kumar Singh , Shesh Mani Pandey
IPC分类号： H01L23/532 , H01L21/768 , H01L21/02 , H01L23/522
摘要： The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures with reduced capacitance and methods of manufacture. The method includes: forming one or more lower metal lines in a dielectric material; forming an airgap structure in an upper dielectric material above the one or more lower metal lines, by subjecting material to a curing process; and forming an upper metal structure above the airgap structure.

3. 发明申请

US20190131432A1 SINGLE-CURVATURE CAVITY FOR SEMICONDUCTOR EPITAXY 审中-公开
公开(公告)号：US20190131432A1
公开(公告)日：2019-05-02
申请号：US15795833
申请日：2017-10-27
申请人： GLOBALFOUNDRIES Inc.
发明人： Yi Qi , Sang Woo Lim , Kyung-Bum Koo , Alina Vinslava , Pei Zhao , Zhenyu Hu , Hsien-Ching Lo , Joseph F. Shepard, JR. , Shesh Mani Pandey
IPC分类号： H01L29/66 , H01L21/02 , H01L21/3065 , H01L29/08 , H01L29/161 , H01L29/16 , H01L29/165 , H01L29/78
CPC分类号： H01L29/66636 , H01L21/02529 , H01L21/02532 , H01L21/3065 , H01L21/845 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

4. 发明申请

US20190097019A1 FIELD-EFFECT TRANSISTORS WITH FINS FORMED BY A DAMASCENE-LIKE PROCESS 审中-公开
公开(公告)号：US20190097019A1
公开(公告)日：2019-03-28
申请号：US15712748
申请日：2017-09-22
申请人： GLOBALFOUNDRIES Inc.
发明人： Wei Zhao , Haiting Wang , David P. Brunco , Jiehui Shu , Shesh Mani Pandey , Jinping Liu , Scott Beasor
IPC分类号： H01L29/66 , H01L21/02 , H01L29/417 , H01L21/762
CPC分类号： H01L29/6681 , H01L21/02532 , H01L21/02636 , H01L21/02664 , H01L21/76224 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/1054 , H01L29/41791 , H01L29/66795
摘要： Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

5. 发明授权

US10164099B2 Device with diffusion blocking layer in source/drain region 有权
公开(公告)号：US10164099B2
公开(公告)日：2018-12-25
申请号：US15889367
申请日：2018-02-06
申请人： GLOBALFOUNDRIES Inc.
发明人： Shesh Mani Pandey , Pei Zhao , Baofu Zhu , Francis L. Benistant
IPC分类号： H01L29/78 , H01L29/08 , H01L29/16 , H01L29/165 , H01L29/66
摘要： One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.

6. 发明申请

US20180175198A1 DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION 审中-公开
公开(公告)号：US20180175198A1
公开(公告)日：2018-06-21
申请号：US15889367
申请日：2018-02-06
申请人： GLOBALFOUNDRIES Inc.
发明人： Shesh Mani Pandey , Pei Zhao , Baofu Zhu , Francis L. Benistant
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L29/165 , H01L29/16
CPC分类号： H01L29/7848 , H01L29/0847 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要： One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.

7. 发明授权

US09966313B2 FinFET device and method of manufacturing 有权
公开(公告)号：US09966313B2
公开(公告)日：2018-05-08
申请号：US15229431
申请日：2016-08-05
申请人： GLOBALFOUNDRIES Inc.
发明人： Shesh Mani Pandey , Baofu Zhu , Srikanth Balaji Samavedam
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823481 , H01L21/823431 , H01L21/823468 , H01L27/0886 , H01L29/66818 , H01L29/7853
摘要： A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.

8. 发明申请

US20170229578A1 DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION 有权
公开(公告)号：US20170229578A1
公开(公告)日：2017-08-10
申请号：US15019273
申请日：2016-02-09
申请人： GLOBALFOUNDRIES Inc.
发明人： Shesh Mani Pandey , Pei Zhao , Baofu Zhu , Francis L. Benistant
IPC分类号： H01L29/78 , H01L29/66 , H01L29/165 , H01L29/08 , H01L29/16
CPC分类号： H01L29/7848 , H01L29/0847 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要： A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.

9. 发明授权

US09679990B2 Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication 有权
公开(公告)号：US09679990B2
公开(公告)日：2017-06-13
申请号：US14454778
申请日：2014-08-08
申请人： GLOBALFOUNDRIES Inc.
发明人： Edmund Kenneth Banghart , Mitsuhiro Togo , Shesh Mani Pandey
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/7851 , H01L21/26513 , H01L29/0847 , H01L29/1033 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.

10. 发明授权

US09419082B2 Source/drain profile engineering for enhanced p-MOSFET 有权
标题翻译：增强型p-MOSFET的源极/漏极配置文件工程
公开(公告)号：US09419082B2
公开(公告)日：2016-08-16
申请号：US14259726
申请日：2014-04-23
申请人： GLOBALFOUNDRIES Inc.
发明人： Shiv Kumar Mishra , Zhiqing Li , Scott Beasor , Shesh Mani Pandey
IPC分类号： H01L21/22 , H01L29/36 , H01L29/16 , H01L29/78 , H01L21/02 , H01L29/66
CPC分类号： H01L29/365 , H01L21/02532 , H01L21/02579 , H01L29/105 , H01L29/1054 , H01L29/16 , H01L29/66477 , H01L29/66568 , H01L29/78
摘要： P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film. Methods of forming the pMOSFET's include: providing a semiconductor substrate; depositing a SiGe film on the semiconductor substrate, thereby forming a lower interface of the SiGe film in contact with the semiconductor substrate, and an upper surface of the SiGe film; and doping the SiGe film with boron to form a SiGe film having a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.
摘要翻译：提供了P型金属氧化物半导体场效应晶体管（pMOSFET），包括pMOSFET的半导体器件和形成pMOSFET的方法。 pMOSFET包括具有与半导体衬底和上表面接触的较低界面的硅 - 锗（SiGe）膜，并且SiGe膜具有梯度硼掺杂分布，其中硼含量在硼的宽度的大部分上向上增加 SiGe膜的下界面与SiGe膜的上表面之间的掺杂SiGe膜。形成pMOSFET的方法包括：提供半导体衬底; 在半导体衬底上沉积SiGe膜，从而形成与半导体衬底接触的SiGe膜的下界面和SiGe膜的上表面; 并且用硼掺杂SiGe膜以形成具有渐变硼掺杂分布的SiGe膜，其中硼含量在SiGe膜的下界面和SiGe的上表面之间的硼掺杂SiGe膜的宽度的大部分上向上增加电影。

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