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1. 发明授权

US09786607B2 Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer 有权
公开(公告)号：US09786607B2
公开(公告)日：2017-10-10
申请号：US15277732
申请日：2016-09-27
申请人： International Business Machines Corporation , GlobalFoundries, Inc.
发明人： Su Chen Fan , Sukwon Hong , William J. Taylor, Jr.
IPC分类号： H01L23/48 , H01L23/535 , H01L21/768 , H01L23/532 , H01L23/528
CPC分类号： H01L23/535 , H01L21/76802 , H01L21/76829 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L21/76895 , H01L23/528 , H01L23/53238 , H01L23/53295
摘要： An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

2. 发明授权

US08728885B1 Methods of forming a three-dimensional semiconductor device with a nanowire channel structure 有权
标题翻译：形成具有纳米线通道结构的三维半导体器件的方法
公开(公告)号：US08728885B1
公开(公告)日：2014-05-20
申请号：US13728438
申请日：2012-12-27
申请人： GLOBALFOUNDRIES Inc.
发明人： Daniel T. Pham , Jody Fronheiser , William J. Taylor, Jr.
IPC分类号： H01L29/94
CPC分类号： H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/7846 , H01L29/78696
摘要： One method herein includes forming a plurality of spaced-apart trenches that extend at least partially into a semiconducting substrate, wherein the trenches define a fin structure comprised of first and second layers of semiconducting material, wherein the first layer of semiconducting material is selectively etchable relative to the substrate and the second layer of semiconducting material, forming a sacrificial gate structure above the fin, wherein the gate structure includes a gate insulation layer and a gate electrode, forming a sidewall spacer adjacent the gate structure, performing an etching process to remove the sacrificial gate structure, thereby defining a gate cavity, performing at least one selective etching process to selectively remove the first layer of semiconducting material relative to the second layer of semiconducting material within the gate cavity, thereby defining a space between the second semiconducting material and the substrate, and forming a final gate structure in the gate cavity.
摘要翻译：这里的一种方法包括形成多个间隔开的沟槽，其至少部分地延伸到半导体衬底中，其中沟槽限定由第一和第二半导体材料层组成的鳍结构，其中第一层半导体材料是相对于可选择地蚀刻的到所述衬底和所述第二半导体材料层，在所述鳍片之上形成牺牲栅极结构，其中所述栅极结构包括栅极绝缘层和栅电极，形成邻近所述栅极结构的侧壁隔离层，执行蚀刻工艺以去除所述栅极结构牺牲栅极结构，从而限定栅极腔，执行至少一个选择性蚀刻工艺，以相对于栅极腔内的第二半导体材料层选择性地去除第一半导体材料层，由此限定第二半导体材料与第二半导体材料之间的空间衬底，并形成最终的门结构在门洞里。

3. 发明授权

US09461171B2 Methods of increasing silicide to epi contact areas and the resulting devices 有权
标题翻译：将硅化物增加到epi接触区域的方法以及所得到的器件
公开(公告)号：US09461171B2
公开(公告)日：2016-10-04
申请号：US14283636
申请日：2014-05-21
申请人： GLOBALFOUNDRIES Inc.
发明人： Ruilong Xie , Hoon Kim , Naim Moumen , Chanro Park , William J. Taylor, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L29/417 , H01L29/08 , H01L21/768 , H01L21/285 , H01L23/485 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/28518 , H01L21/28525 , H01L21/76805 , H01L21/76897 , H01L23/485 , H01L29/0847 , H01L29/165 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer.
摘要翻译：所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，执行外延沉积工艺以在器件的源极/漏极区域中的有源区上形成外延半导体材料，进行蚀刻处理外延半导体材料以去除外延半导体材料的一部分，以便限定外延半导体材料中的至少一个外延凹部，在外延半导体材料的上表面上形成金属硅化物层，并且在至少一个 epi凹槽，并且形成导电耦合到金属硅化物层的导电结构。

4. 发明授权

US09202918B2 Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices 有权
标题翻译：在FinFET半导体器件上形成应力层的方法和所得到的器件
公开(公告)号：US09202918B2
公开(公告)日：2015-12-01
申请号：US14030540
申请日：2013-09-18
申请人： GLOBALFOUNDRIES Inc.
发明人： Ruilong Xie , Ryan Ryoung-han Kim , William J. Taylor, Jr.
IPC分类号： H01L21/00 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7846 , H01L23/5226 , H01L23/528 , H01L29/0653 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： One method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess and forming a stress-inducing material layer above the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure, a stress-inducing material layer formed above the buried fin contact structures and a source/drain contact that extends through the stress-inducing material layer.
摘要翻译：一种方法包括形成具有在衬底上方的凹陷的凸起的隔离结构，在鳍的上方形成栅极结构，在凹槽内形成多个间隔开的隐埋翅片接触结构，并在埋入鳍接触件上方形成应力诱导材料层结构。一个装置包括位于栅极结构的相对侧上的凸起的隔离结构的凹部内的多个间隔开的埋入式翅片接触结构，形成在埋入式翅片接触结构上方的应力诱导材料层和源极/漏极接点，延伸穿过应力诱导材料层。

5. 发明授权

US08962413B1 Methods of forming spacers on FinFETs and other semiconductor devices 有权
标题翻译：在FinFET和其他半导体器件上形成间隔物的方法
公开(公告)号：US08962413B1
公开(公告)日：2015-02-24
申请号：US14524076
申请日：2014-10-27
申请人： GLOBALFOUNDRIES Inc.
发明人： Xiuyu Cai , Ruilong Xie , William J. Taylor, Jr.
IPC分类号： H01L21/336 , H01L21/762 , H01L21/02 , H01L21/8234
CPC分类号： H01L29/0649 , H01L21/02263 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/66795 , H01L29/7851
摘要： Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.
摘要翻译：这里公开了在FinFET和其它半导体器件上形成间隔物的各种方法。在一个示例中，该方法包括在限定鳍片的半导体衬底中形成多个间隔开的沟槽，在沟槽中形成覆盖翅片下部的第一绝缘材料层，但暴露鳍片的上部并且在所述暴露的所述翅片的上部上形成第二绝缘材料层。所述方法还包括在所述鳍的上表面和所述沟槽的底部中选择性地形成电介质材料，在所述器件的栅极结构之上和在所述鳍上方和所述沟槽中的所述电介质材料之上沉积间隔物材料层，以及对所述隔离层材料层进行蚀刻处理以限定邻近所述栅极结构定位的侧壁间隔物。

6. 发明授权

US09318552B2 Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices 有权
标题翻译：形成具有较大金属硅化物接触面积的半导体器件的导电接触结构的方法以及所得到的器件
公开(公告)号：US09318552B2
公开(公告)日：2016-04-19
申请号：US14283404
申请日：2014-05-21
申请人： GLOBALFOUNDRIES Inc.
发明人： Ruilong Xie , William J. Taylor, Jr. , Ajey Poovannummoottil Jacob
IPC分类号： H01L21/8238 , H01L21/8234 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/417 , H01L29/49
CPC分类号： H01L29/78618 , H01L21/823418 , H01L21/823431 , H01L21/823814 , H01L21/823821 , H01L29/0669 , H01L29/0673 , H01L29/41783 , H01L29/41791 , H01L29/42376 , H01L29/42392 , H01L29/4966 , H01L29/66439 , H01L29/66545 , H01L29/66553 , H01L29/6681 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor device, the first epi semiconductor material having a first lateral width at an upper surface thereof, forming a second epi semiconductor material on the first epi semiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second epi semiconductor material has a second lateral width at an upper surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper surface of the second epi semiconductor material.
摘要翻译：本文公开的一种说明性方法包括在晶体管器件的源极/漏极区域中形成第一外延半导体材料，第一外延半导体材料在其上表面具有第一横向宽度，形成第二外延半导体材料在所述第一外延半导体材料上以及所述器件的所述侧壁间隔物中的至少一部分栅极帽层或所述侧壁间隔物中的至少一部分，其中所述第二外延半导体材料在其上表面处具有大于第一横向宽度，并且在第二外延半导体材料的上表面上形成金属硅化物区域。

7. 发明授权

US09231051B2 Methods of forming spacers on FinFETs and other semiconductor devices 有权
公开(公告)号：US09231051B2
公开(公告)日：2016-01-05
申请号：US14579428
申请日：2014-12-22
申请人： GLOBALFOUNDRIES Inc.
发明人： Xiuyu Cai , Ruilong Xie , William J. Taylor, Jr.
IPC分类号： H01L21/8234 , H01L29/06 , H01L29/66 , H01L29/78 , H01L21/02 , H01L21/762 , H01L27/088
CPC分类号： H01L29/0649 , H01L21/02263 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/66795 , H01L29/7851
摘要： Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.

8. 发明授权

US09153694B2 Methods of forming contact structures on finfet semiconductor devices and the resulting devices 有权
标题翻译：在finfet半导体器件和所产生的器件上形成接触结构的方法
公开(公告)号：US09153694B2
公开(公告)日：2015-10-06
申请号：US14017781
申请日：2013-09-04
申请人： GLOBALFOUNDRIES Inc.
发明人： Ruilong Xie , Ryan Ryoung-Han Kim , William J. Taylor, Jr.
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L27/0886 , H01L29/0642 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/7851
摘要： A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface of the recess and forming at least one source/drain contact structure for each of the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure. The upper surface of each of the buried fin contact structures is positioned below an upper surface of the raised isolation structure and an outer perimeter surface of each of the buried fin contact structures contacts at least a portion of an interior perimeter surface of the recess.
摘要翻译：一种方法包括形成具有在衬底上方的凹陷的凸起的隔离结构，在鳍的上方形成栅极结构，在凹槽内形成多个间隔开的隐埋翅片接触结构，其具有外周表面，该外周表面接触至少部分凹陷的内周边表面，并形成用于每个埋入鳍接触结构的至少一个源极/漏极接触结构。一个装置包括位于栅极结构的相对侧上的凸起的隔离结构中的凹部内的多个间隔开的埋入式翅片接触结构。每个埋入式翅片接触结构的上表面位于凸起隔离结构的上表面的下方，并且每个埋入式翅片接触结构的外周表面与凹部的内周边表面的至少一部分接触。

9. 发明申请

US20150255555A1 METHODS OF FORMING A NON-PLANAR ULTRA-THIN BODY DEVICE 审中-公开
标题翻译：形成非平面超薄体器件的方法
公开(公告)号：US20150255555A1
公开(公告)日：2015-09-10
申请号：US14197686
申请日：2014-03-05
申请人： GLOBALFOUNDRIES INC.
发明人： Ruilong Xie , Ajey Poovannummoottil Jacob , Michael Hargrove , William J. Taylor, Jr.
IPC分类号： H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/1054 , H01L29/785
摘要： One illustrative method disclosed herein involves, among other things, forming a first epi semiconductor material on the exposed opposite sidewalls of a fin to thereby define a semiconductor body, performing at least one etching process to remove at least a portion of the substrate portion of the fin positioned between the first epi semiconductor materials positioned on the opposite sidewalls of the fin and to thereby define a back-gate cavity, forming a back-gate insulating material within the back-gate cavity and on the first epi semiconductor materials, forming a back-gate electrode on the back-gate insulation material within the back-gate cavity and forming a gate structure comprised of a gate insulation layer and a gate electrode around the semiconductor bodies.
摘要翻译：本文公开的一种说明性方法除其他外包括在鳍的暴露的相对侧壁上形成第一外延半导体材料，从而限定半导体本体，执行至少一个蚀刻工艺以去除衬底部分的至少一部分翅片定位在位于翅片的相对侧壁上的第一外延半导体材料之间，从而限定背栅腔，在背栅腔内和第一外延半导体材料上形成背栅绝缘材料，形成背在后栅极腔内的背栅极绝缘材料上形成栅极电极，并且形成由半导体本体周围的栅极绝缘层和栅极电极构成的栅极结构。

10. 发明授权

US09583442B2 Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer 有权
标题翻译：互连结构包括中间线（MOL）金属层局部互连在蚀刻停止层上
公开(公告)号：US09583442B2
公开(公告)日：2017-02-28
申请号：US14753407
申请日：2015-06-29
申请人： International Business Machines Corporation , GlobalFoundries, Inc.
发明人： Su Chen Fan , Sukwon Hong , William J. Taylor, Jr.
IPC分类号： H01L21/4763 , H01L23/535 , H01L21/768 , H01L23/532
CPC分类号： H01L23/535 , H01L21/76802 , H01L21/76829 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L21/76895 , H01L23/528 , H01L23/53238 , H01L23/53295
摘要： An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.
摘要翻译：互连结构包括在半导体衬底的上表面上的绝缘体堆叠。绝缘体堆叠包括具有嵌入其中的至少一个半导体器件的第一绝缘体层和插入在第一绝缘体层和第二绝缘体层之间的蚀刻停止层。至少一个导电局部接触件延伸穿过第二绝缘体层，蚀刻停止层和与第一半导体器件接触的第一绝缘体层中的每一个。所述互连结构还包括设置在所述蚀刻停止层上并抵靠所述至少一个导电性局部接触的至少一个第一层接触元件。

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