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1. 发明申请

US20170330896A1 INTEGRATED CIRCUITS WITH DEEP AND ULTRA SHALLOW TRENCH ISOLATIONS AND METHODS FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20170330896A1
公开(公告)日：2017-11-16
申请号：US15151564
申请日：2016-05-11
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Guan Huei See , Rui Tze Toh , Shaoqiang Zhang , Purakh Raj Verma
IPC分类号： H01L27/12 , H01L21/84 , H01L29/06 , H01L29/49
CPC分类号： H01L27/1203 , H01L21/28123 , H01L21/84 , H01L29/0649 , H01L29/402 , H01L29/4975 , H01L29/66901 , H01L29/8086
摘要： Integrated circuits and methods of producing the same are provided herein. In accordance with an exemplary embodiment, an integrated circuit includes an SOI substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer. A source is defined within the active layer, and a gate well is also defined within the active layer. A first ultra shallow trench isolation extends into the active layer, where a first portion of the active layer is positioned between the first ultra shallow trench isolation and the buried insulator layer. The first ultra shallow trench isolation is positioned between the source and the gate well.

2. 发明授权

US09673084B2 Isolation scheme for high voltage device 有权
公开(公告)号：US09673084B2
公开(公告)日：2017-06-06
申请号：US14958873
申请日：2015-12-03
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Kun Liu , Francis Benistant , Ming Li , Namchil Mun , Shiang Yang Ong , Purakh Raj Verma
IPC分类号： H01L21/762 , H01L21/763 , H01L29/06 , H01L29/78
CPC分类号： H01L21/76229 , H01L21/76283 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L27/0922 , H01L29/0649 , H01L29/0692 , H01L29/66681 , H01L29/78 , H01L29/7816
摘要： Semiconductor device isolation and method of forming thereof are presented. A base substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate while an epitaxial layer is formed over the buried layer. First and second type deep trench isolation (DTI) structures which extend from surface of the epitaxial layer to a portion of the base substrate are formed to isolate different device regions defined in the substrate. The first and second type DTI structures have different width dimensions. Shallow trench isolation (STI) regions are formed in the epitaxial layer and at least one transistor is formed on the epitaxial layer. The first and second type DTI structures effectively isolate the transistor from other device regions and enhances the breakdown voltage.

3. 发明授权

US09054133B2 High voltage trench transistor 有权
标题翻译：高压沟槽晶体管
公开(公告)号：US09054133B2
公开(公告)日：2015-06-09
申请号：US13948178
申请日：2013-07-23
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Yemin Dong , Liang Yi , Zhanfeng Liu , Purakh Raj Verma , Ramadas Nambatyathu
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/40 , H01L29/423 , H01L27/092 , H01L29/417 , H01L29/06 , H01L29/08
CPC分类号： H01L29/063 , H01L27/0922 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66704 , H01L29/66719 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7825
摘要： A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region.
摘要翻译：公开了一种形成装置的方法。提供了用设备区域定义的衬底。在沟槽中形成具有栅极电极，第一和第二栅极电介质层的栅极。沟槽具有上沟槽部分和下沟槽部分。在沟槽中形成场板。形成第一和第二扩散区。栅极从第二扩散区域移位。

4. 发明申请

US20150097256A1 SEMICONDUCTOR DEVICES INCLUDING AVALANCHE PHOTODETECTOR DIODES INTEGRATED ON WAVEGUIDES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：包含在波导中集成的AVALANCHE光电二极管的半导体器件及其制造方法
公开(公告)号：US20150097256A1
公开(公告)日：2015-04-09
申请号：US14045180
申请日：2013-10-03
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Kah-Wee Ang , Purakh Raj Verma
IPC分类号： H01L31/107 , H01L31/0232 , H01L31/18
CPC分类号： H01L31/1075 , G02B6/00 , G02B6/42 , H01L31/02327 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a trench into a waveguide layer in a detector region of a semiconductor substrate. An avalanche photodetector diode is formed about the trench. Forming the avalanche photodetector diode includes forming a multiplication region in the waveguide layer laterally adjacent to the trench. An absorption region is formed at least partially disposed in the trench.
摘要翻译：提供了用于制造半导体器件的半导体器件和方法。在一个示例中，制造半导体器件的方法包括将沟槽蚀刻到半导体衬底的检测器区域中的波导层中。围绕沟槽形成雪崩光电二极管。形成雪崩光电检测器二极管包括在波导层中横向相邻于沟槽形成乘法区域。形成至少部分地设置在沟槽中的吸收区域。

5. 发明授权

US08853783B2 ESD protection circuit 有权
标题翻译： ESD保护电路
公开(公告)号：US08853783B2
公开(公告)日：2014-10-07
申请号：US13669409
申请日：2012-11-05
申请人： GlobalFoundries Singapore Pte. Ltd.
发明人： Da-Wei Lai , Ming Li , Jeoung Mo Koo , Purakh Raj Verma
IPC分类号： H01L23/62 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78 , H01L27/027 , H01L29/0623 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/456 , H01L29/4933 , H01L29/7816 , H01L29/7835
摘要： A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well.
摘要翻译：公开了一种包括由具有ESD保护电路的器件区限定的衬底的器件。 ESD保护电路具有晶体管。晶体管包括具有第一和第二侧面的栅极。第一扩散区域邻近栅极的第一侧设置，并且第二扩散区域设置在远离栅极的第二侧移位的器件区域中。第一和第二扩散区域包括第一极性类型的掺杂剂。漂移隔离区域设置在栅极和第二扩散区域之间。第一装置阱包围装置区域，第二装置井设置在第一装置井内。具有第一极性类型的掺杂剂的漏极阱设置在第二扩散区域的下方和第一器件阱内。

6. 发明授权

US10347710B2 Thin film resistor methods of making contacts 有权
公开(公告)号：US10347710B2
公开(公告)日：2019-07-09
申请号：US15446079
申请日：2017-03-01
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Purakh Raj Verma , Kemao Lin
IPC分类号： H01L49/02 , H01L21/768 , H01L21/3205 , H01L23/522 , H01L23/532
摘要： A method for forming a thin film resistor (TFR) without via penetration and the resulting device are provided. Embodiments include forming a first ILD over a substrate; forming a second ILD over the first ILD; forming a first metal layer in the second ILD; forming a first nitride layer over the second ILD and the first metal layer; forming a third ILD over the first nitride layer; forming vias through the third ILD and the first nitride layer, coupled to the first metal layer; forming a TFR layer over two of the vias and the third ILD between the two vias; forming a second nitride layer over the TFR layer and the third ILD; forming a fourth ILD over the second nitride layer; and forming a second metal layer in the fourth ILD and the second nitride layer.

7. 发明授权

US09721969B2 Creation of wide band gap material for integration to SOI thereof 有权
公开(公告)号：US09721969B2
公开(公告)日：2017-08-01
申请号：US14788703
申请日：2015-06-30
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Purakh Raj Verma , Shaoqiang Zhang
IPC分类号： H01L21/82 , H01L27/12 , H01L29/16 , H01L29/20 , H01L21/84 , H01L21/8252
CPC分类号： H01L27/1207 , H01L21/8213 , H01L21/8252 , H01L21/84 , H01L29/1608 , H01L29/20 , H01L29/2003
摘要： Devices and methods for forming a device are presented. The method for forming the device includes providing a support substrate having first crystal orientation. A trap rich layer is formed on the support substrate. An insulator layer is formed over a top surface of the trap rich layer. The method further includes forming a top surface layer having second crystal orientation on the insulator layer. The support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions. A transistor is formed in the top surface layer in the first device region and a wide band gap device is formed in the second device region.

8. 发明授权

US09525061B2 Semiconductor device including an n-well structure 有权
公开(公告)号：US09525061B2
公开(公告)日：2016-12-20
申请号：US14794843
申请日：2015-07-09
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Jeoung Mo Koo , Purakh Raj Verma , Guowei Zhang
IPC分类号： H01L29/78 , H01L29/06 , H01L29/10 , H01L21/265 , H01L21/762 , H01L21/8238
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/76224 , H01L21/823892 , H01L29/0653 , H01L29/10 , H01L29/1079 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7835
摘要： A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer.

9. 发明授权

US09230990B2 Silicon-on-insulator integrated circuit devices with body contact structures 有权
标题翻译：具有体接触结构的绝缘体上硅集成电路器件
公开(公告)号：US09230990B2
公开(公告)日：2016-01-05
申请号：US14253629
申请日：2014-04-15
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shaoqiang Zhang , Guan Huei See , Purakh Raj Verma
IPC分类号： H01L27/01 , H01L27/12 , H01L29/00 , H01L21/768 , H01L29/10 , H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/76229 , H01L21/76283 , H01L21/76897 , H01L21/823475 , H01L27/0207 , H01L29/1087 , H01L29/66575 , H01L29/7824 , H01L29/78615
摘要： Silicon-on-insulator integrated circuits including body contact structures and methods for fabricating the same are disclosed. A method for fabricating a silicon-on-insulator integrated circuit includes filling a plurality of first and second shallow isolation trenches with an insulating material to form plurality of first and second shallow trench isolation (STI) structures, and forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least two of the plurality of second STI structures and a second portion disposed in between the at least two of the plurality of second STI structures. The method further includes forming contact plugs to a body contact region of the semiconductor layer. The body contact region comprises a portion of the semiconductor layer between at least one of the plurality of first STI structures and at least one of the plurality of second STI structures.
摘要翻译：公开了包括体接触结构的绝缘体上硅集成电路及其制造方法。一种用于制造绝缘体上硅集成电路的方法包括用绝缘材料填充多个第一和第二浅隔离沟槽以形成多个第一和第二浅沟槽隔离（STI）结构，以及在半导体上形成栅极结构层，其包括布置在所述多个第二STI结构中的至少两个上方并且平行于所述多个第二STI结构中的至少两个的第一部分和设置在所述多个第二STI结构中的所述至少两个之间的第二部分。该方法还包括将接触塞形成到半导体层的体接触区域。身体接触区域包括多个第一STI结构中的至少一个与多个第二STI结构中的至少一个之间的半导体层的一部分。

10. 发明授权

US09209297B2 Integration of trench MOS with low voltage integrated circuits 有权
标题翻译：沟槽MOS与低压集成电路的集成
公开(公告)号：US09209297B2
公开(公告)日：2015-12-08
申请号：US14083557
申请日：2013-11-19
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Purakh Raj Verma , Yi Liang , Dong Yemin
IPC分类号： H01L21/8238 , H01L29/78 , H01L27/092 , H01L29/66 , H01L29/417 , H01L29/423
CPC分类号： H01L29/7827 , H01L21/823814 , H01L27/0922 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7833
摘要： A high voltage trench MOS and its integration with low voltage integrated circuits. Embodiments include forming a first trench in a substrate, the first trench having a first width; forming a first oxide layer on side surfaces of the first trench; forming a second trench in the substrate, below the first trench, the second trench having a second width less than the first width; forming a second oxide layer on side and bottom surfaces of the second trench; forming spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on the side surfaces and a top surface of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.
摘要翻译：高压沟槽MOS及其与低压集成电路的集成。实施例包括在衬底中形成第一沟槽，第一沟槽具有第一宽度; 在所述第一沟槽的侧表面上形成第一氧化物层; 在所述衬底中形成第二沟槽，在所述第一沟槽下方，所述第二沟槽具有小于所述第一宽度的第二宽度; 在所述第二沟槽的侧表面和底表面上形成第二氧化物层; 在第一和第二沟槽的侧面上形成间隔物; 从所述间隔件之间的所述第二沟槽的底表面去除所述第二氧化物层的一部分; 用第一多晶硅填充第一和第二沟槽以形成漏区; 去除间隔物，暴露第一多晶硅的侧表面; 在所述第一多晶硅的侧表面和顶表面上形成第三氧化物层; 以及用第二多晶硅硅填充所述第一和第二沟槽的剩余部分，以在所述漏极区域的每一侧上形成栅极区域。

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