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1. 发明申请

US20100271071A1 Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks 有权
标题翻译：多层半导体堆叠的通用层间互连
公开(公告)号：US20100271071A1
公开(公告)日：2010-10-28
申请号：US12431259
申请日：2009-04-28
申请人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
发明人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
IPC分类号： H01L25/00 , G06F17/50
CPC分类号： G06F17/5068 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01019 , H01L2924/01087 , H01L2224/05599 , H01L2224/05099
摘要： A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack.
摘要翻译：电路布置和方法利用多层半导体堆叠中的通用的标准化层间互连，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。基于每个电路层中的层间界面区域的标准化布置以及与层间总线相关联的电导体的标准化布置，每个电路层可以使用标准化模板来设计，在该模板上设计实现已经提供了层间总线，从而简化了电路层设计和功能单元与层间总线的互连。此外，可以在半导体堆叠内定义垂直取向的超节点，以提供多个独立运行的节点，其具有布置在堆叠的多个电路层中的功能单元。

2. 发明申请

US20130009324A1 UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS 有权
标题翻译：用于多层半导体堆叠的通用层间互连
公开(公告)号：US20130009324A1
公开(公告)日：2013-01-10
申请号：US13618600
申请日：2012-09-14
申请人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
发明人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
IPC分类号： H01L23/522 , H01L23/48 , G06F17/50
CPC分类号： G06F17/5068 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01019 , H01L2924/01087 , H01L2224/05599 , H01L2224/05099
摘要： An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.
摘要翻译：一种装置，程序产品和方法有助于在多层半导体堆叠中结合通用的标准化层间互连的多层电路装置的设计，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。

3. 发明授权

US09495498B2 Universal inter-layer interconnect for multi-layer semiconductor stacks 有权
标题翻译：用于多层半导体堆叠的通用层间互连
公开(公告)号：US09495498B2
公开(公告)日：2016-11-15
申请号：US13618600
申请日：2012-09-14
申请人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
发明人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
IPC分类号： H01L25/00 , G06F17/50 , H01L25/065
CPC分类号： G06F17/5068 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01019 , H01L2924/01087 , H01L2224/05599 , H01L2224/05099
摘要： An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.
摘要翻译：一种装置，程序产品和方法有助于在多层半导体堆叠中结合通用的标准化层间互连的多层电路装置的设计，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。

4. 发明授权

US08330489B2 Universal inter-layer interconnect for multi-layer semiconductor stacks 有权
标题翻译：用于多层半导体堆叠的通用层间互连
公开(公告)号：US08330489B2
公开(公告)日：2012-12-11
申请号：US12431259
申请日：2009-04-28
申请人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
发明人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
IPC分类号： H01L25/00
CPC分类号： G06F17/5068 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01019 , H01L2924/01087 , H01L2224/05599 , H01L2224/05099
摘要： A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack.
摘要翻译：电路布置和方法利用多层半导体堆叠中的通用的标准化层间互连，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。基于每个电路层中的层间界面区域的标准化布置以及与层间总线相关联的电导体的标准化布置，每个电路层可以使用标准化模板来设计，在该模板上设计实现已经提供了层间总线，从而简化了电路层设计和功能单元与层间总线的互连。此外，可以在半导体堆叠内定义垂直取向的超节点，以提供多个独立运行的节点，其具有布置在堆叠的多个电路层中的功能单元。

5. 发明申请

US20120198406A1 UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS 审中-公开
标题翻译：用于多层半导体堆叠的通用层间互连
公开(公告)号：US20120198406A1
公开(公告)日：2012-08-02
申请号：US13422566
申请日：2012-03-16
申请人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
发明人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01019 , H01L2924/01087 , H01L2224/05599 , H01L2224/05099
摘要： An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.
摘要翻译：一种装置，程序产品和方法有助于在多层半导体堆叠中结合通用的标准化层间互连的多层电路装置的设计，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。

6. 发明授权

US06566281B1 Nitrogen-rich barrier layer and structures formed 失效
标题翻译：形成富氮阻挡层和结构
公开(公告)号：US06566281B1
公开(公告)日：2003-05-20
申请号：US08982150
申请日：1997-12-01
申请人： Douglas Andrew Buchanan , Matthew Warren Copel , Fenton Read McFeely , Patrick Ronald Varekamp , Mark Monroe Banaszak Holl , Kyle Erik Litz
发明人： Douglas Andrew Buchanan , Matthew Warren Copel , Fenton Read McFeely , Patrick Ronald Varekamp , Mark Monroe Banaszak Holl , Kyle Erik Litz
IPC分类号： H01L2131
CPC分类号： H01L21/3145 , H01L21/823857
摘要： The present invention discloses a method for forming a layer of nitrogen and silicon containing material on a substrate by first providing a heated substrate and then flowing a gas which has silicon and nitrogen atoms but no carbon atoms in the same molecule over said heated substrate at a pressure of not higher than 500 Torr, such that a layer of nitrogen and silicon containing material is formed on the surface. The present invention is further directed to a composite structure that includes a substrate and a layer of material containing nitrogen and silicon but not carbon overlying the substrate for stopping chemical species from reaching the substrate. The present invention is further directed to a structure that includes a semiconducting substrate, a gate insulator on the substrate, a nitrogen-rich layer on top of the gate insulator, and a gate electrode on the nitrogen-rich layer, wherein the nitrogen-rich layer blocks diffusion of contaminating species from the gate electrode to the gate insulator.
摘要翻译：本发明公开了一种在衬底上形成含氮和硅的材料层的方法，首先提供加热的衬底，然后在相同分子中将具有硅和氮原子但不含碳原子的气体在所述加热的衬底上以压力不高于500托，使得在表面上形成含氮和硅的材料层。本发明还涉及一种复合结构，该复合结构包括衬底和含有氮和硅而不是覆盖衬底的碳的材料层，用于阻止化学物质到达衬底。本发明还涉及一种结构，其包括半导体衬底，衬底上的栅极绝缘体，栅极绝缘体顶部的富氮层和富氮层上的栅电极，其中富氮污染物质从栅极扩散到栅极绝缘体。

7. 发明授权

US06245616B1 Method of forming oxynitride gate dielectric 失效
标题翻译：形成氮氧化物栅极电介质的方法
公开(公告)号：US06245616B1
公开(公告)日：2001-06-12
申请号：US09226369
申请日：1999-01-06
申请人： Douglas Andrew Buchanan , Matthew Warren Copel , Patrick Ronald Varekamp
发明人： Douglas Andrew Buchanan , Matthew Warren Copel , Patrick Ronald Varekamp
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： A method for forming an oxynitride gate dielectric in a semiconductor device and gate dielectric structure formed by the method are disclosed. In the method, an oxynitride layer is first formed on a silicon surface and then re-oxidized with a gas mixture containing oxygen and at least one halogenated species such that an oxynitride layer with a controlled nitrogen profile and a layer of substantially silicon dioxide formed underneath the oxynitride film is obtained. The oxynitride film layer can be formed by either contacting a surface of silicon with at least one gas that contains nitrogen and/or oxygen at a temperature of not less than 500° C. or by a chemical vapor deposition technique. The re-oxidation process may be carried out by a thermal process in an oxidizing halogenated atmosphere containing oxygen and a halogenated species such as HCl, CH2Cl2, C2H3Cl3, C2H2Cl2, CH3Cl and CHCl3.
摘要翻译：公开了一种在半导体器件中形成氧氮化物栅极电介质的方法和通过该方法形成的栅极电介质结构。在该方法中，首先在硅表面上形成氧氮化物层，然后用含有氧和至少一种卤化物质的气体混合物再次氧化，使得具有受控氮分布的氧氮化物层和形成在下面的基本上二氧化硅层得到氧氮化物膜。氧氮化物膜层可以通过在不低于500℃的温度下或通过化学气相沉积技术使硅表面与至少一种含有氮和/或氧的气体接触而形成。再氧化过程可以通过在含氧和卤化物质如HCl，CH 2 Cl 2，C 2 H 3 Cl 3，C 2 H 2 Cl 2，CH 3 Cl和CHCl 3的氧化卤化气氛中的热处理进行。

8. 发明授权

US06756646B2 Oxynitride gate dielectric and method of forming 有权
标题翻译：氧氮化物栅极电介质及其形成方法
公开(公告)号：US06756646B2
公开(公告)日：2004-06-29
申请号：US09862372
申请日：2001-05-22
申请人： Douglas Andrew Buchanan , Matthew Warren Copel , Patrick Ronald Varekamp
发明人： Douglas Andrew Buchanan , Matthew Warren Copel , Patrick Ronald Varekamp
IPC分类号： H01L31062
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： A method for forming an oxynitride gate dielectric in a semiconductor device and gate dielectric structure formed by the method are disclosed. In the method, an oxynitride layer is first formed on a silicon surface and then re-oxidized with a gas mixture containing oxygen and at least one halogenated species such that an oxynitride layer with a controlled nitrogen profile and a layer of substantially silicon dioxide formed underneath the oxynitride film is obtained. The oxynitride film layer can be formed by either contacting a surface of silicon with at least one gas that contains. nitrogen and/or oxygen at a temperature of not less than 500° C. or by a chemical vapor deposition technique. The re-oxidation process may be carried out by a thermal process in an oxidizing halogenated atmosphere containing oxygen and a halogenated species such as HCl, CH2Cl2, C2H3Cl3, C2H2Cl2. CH3Cl and CHCl3.
摘要翻译：公开了一种在半导体器件中形成氧氮化物栅极电介质的方法和通过该方法形成的栅极电介质结构。在该方法中，首先在硅表面上形成氧氮化物层，然后用含有氧和至少一种卤化物质的气体混合物再次氧化，使得具有受控氮分布的氧氮化物层和形成在下面的基本上二氧化硅层得到氧氮化物膜。氧氮化物膜层可以通过使硅的表面与至少一种含有气体接触而形成。氮和/或氧的温度不低于500℃，或通过化学气相沉积技术。再氧化过程可以通过在含氧和卤化物质如HCl，CH 2 Cl 2，C 2 H 3 Cl 3，C 2 H 2 Cl 2的氧化卤化气氛中的热处理进行。 CH 3 Cl和CHCl 3。

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