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1. 发明授权

US07676776B2 Spare gate array cell distribution analysis 失效
标题翻译：备用门阵列电池分布分析
公开(公告)号：US07676776B2
公开(公告)日：2010-03-09
申请号：US11767542
申请日：2007-06-25
申请人： Giorgos Stellos Tsapepas , David A. Webber , Michael Hemsley Wood
发明人： Giorgos Stellos Tsapepas , David A. Webber , Michael Hemsley Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081
摘要： A method for determining gate array distribution includes steps or acts of: randomly placing a plurality of test boxes in a logic circuit layout; counting the number of fill cells in each of the plurality of test boxes; recording the count; grouping the plurality of test boxes into two groups: a first group with local clock buffers and a second group without local clock buffers; determining the fill cell percentage of each of the plurality of test boxes; and flagging the test boxes with a poor distribution of gate array cells.
摘要翻译：用于确定门阵列分布的方法包括以下步骤或动作：将多个测试盒随机放置在逻辑电路布局中; 对所述多个测试箱中的每一个中的填充单元的数量进行计数; 记录计数; 将多个测试盒分组成两组：具有本地时钟缓冲器的第一组和不具有本地时钟缓冲器的第二组; 确定所述多个测试盒中的每一个的填充单元百分比; 并标记具有较差的门阵列单元分布的测试盒。

2. 发明申请

US20080320430A1 Spare Gate Array Cell Distribution Analysis 失效
标题翻译：备用阵列细胞分布分析
公开(公告)号：US20080320430A1
公开(公告)日：2008-12-25
申请号：US11767542
申请日：2007-06-25
申请人： Giorgos Stellos Tsapepas , David A. Webber , Michael Hemsley Wood
发明人： Giorgos Stellos Tsapepas , David A. Webber , Michael Hemsley Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081
摘要： A method for determining gate array distribution includes steps or acts of: randomly placing a plurality of test boxes in a logic circuit layout; counting the number of fill cells in each of the plurality of test boxes; recording the count; grouping the plurality of test boxes into two groups: a first group with local clock buffers and a second group without local clock buffers; determining the fill cell percentage of each of the plurality of test boxes; and flagging the test boxes with a poor distribution of gate array cells.
摘要翻译：用于确定门阵列分布的方法包括以下步骤或动作：将多个测试盒随机放置在逻辑电路布局中; 对所述多个测试箱中的每一个中的填充单元的数量进行计数; 记录计数; 将多个测试盒分组成两组：具有本地时钟缓冲器的第一组和不具有本地时钟缓冲器的第二组; 确定所述多个测试盒中的每一个的填充单元百分比; 并标记具有较差的门阵列单元分布的测试盒。

3. 发明授权

US07971162B2 Verification of spare latch placement in synthesized macros 有权
标题翻译：在合成宏中验证备用锁存器位置
公开(公告)号：US07971162B2
公开(公告)日：2011-06-28
申请号：US12032841
申请日：2008-02-18
申请人： Michael Hemsley Wood
发明人： Michael Hemsley Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/68 , G06F2217/72
摘要： A method to assess spare latch placement in a macro, the method comprises steps of: determining a location for each spare latch in the macro; examining local clock buffers associated with the macro to locate any local clock buffers without a spare latch directly attached to clock nets driven by said local clock buffer; measuring a distance between each of the local clock buffers without spare latches and a closest spare latch; running statistics for the local clock buffers from the measuring step; and locating macros with inadequate spare latch placement using the statistics.
摘要翻译：一种评估宏中备用锁存器位置的方法，所述方法包括以下步骤：确定所述宏中每个备用锁存器的位置; 检查与宏相关联的本地时钟缓冲器以定位任何本地时钟缓冲器，而没有直接连接到由所述本地时钟缓冲器驱动的时钟网络的备用锁存器; 测量每个本地时钟缓冲器之间的距离，无需备用锁存器和最近的备用锁存器; 从测量步骤运行本地时钟缓冲区的统计信息; 并使用统计信息查找具有不足的备用锁存位置的宏。

4. 发明授权

US08001411B2 Generating a local clock domain using dynamic controls 失效
标题翻译：使用动态控件生成本地时钟域
公开(公告)号：US08001411B2
公开(公告)日：2011-08-16
申请号：US11859819
申请日：2007-09-24
申请人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
发明人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/3275 , G11C7/22 , G11C7/222 , G11C11/413 , Y02D10/14
摘要： A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.
摘要翻译：一种用于在操作中产生本地时钟域的方法包括以下步骤：在操作期间接收用于逻辑的较慢部分的时钟频率测量; 产生本地信号以指示操作的开始并用作时钟选通信号; 将时钟门控信号锁存到选定的周期; 基于时钟选通信号产生时钟域控制，使得操作在所选择的周期上重新启动; 并且在未锁定的锁存器中传播时钟门控信号多个周期，使得第二操作被限制为被启动直到操作完成。

5. 发明申请

US20090210832A1 Verification of Spare Latch Placement in Synthesized Macros 有权
标题翻译：验证合成宏中的备用锁存位置
公开(公告)号：US20090210832A1
公开(公告)日：2009-08-20
申请号：US12032841
申请日：2008-02-18
申请人： Michael Hemsley Wood
发明人： Michael Hemsley Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/68 , G06F2217/72
摘要： A method to assess spare latch placement in a macro, the method comprises steps of: determining a location for each spare latch in the macro; examining local clock buffers associated with the macro to locate any local clock buffers without a spare latch directly attached to clock nets driven by said local clock buffer; measuring a distance between each of the local clock buffers without spare latches and a closest spare latch; running statistics for the local clock buffers from the measuring step; and locating macros with inadequate spare latch placement using the statistics.
摘要翻译：一种评估宏中备用锁存器位置的方法，所述方法包括以下步骤：确定所述宏中每个备用锁存器的位置; 检查与宏相关联的本地时钟缓冲器以定位任何本地时钟缓冲器，而没有直接连接到由所述本地时钟缓冲器驱动的时钟网络的备用锁存器; 测量每个本地时钟缓冲器之间的距离，无需备用锁存器和最近的备用锁存器; 从测量步骤运行本地时钟缓冲区的统计信息; 并使用统计信息查找具有不足的备用锁存位置的宏。

6. 发明申请

US20090083569A1 Generating a Local Clock Domain Using Dynamic Controls 失效
标题翻译：使用动态控件生成本地时钟域
公开(公告)号：US20090083569A1
公开(公告)日：2009-03-26
申请号：US11859819
申请日：2007-09-24
申请人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
发明人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
IPC分类号： G04F10/00 , H04L7/00 , G06F1/04
CPC分类号： G06F1/04 , G06F1/3275 , G11C7/22 , G11C7/222 , G11C11/413 , Y02D10/14
摘要： A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.
摘要翻译：一种用于在操作中产生本地时钟域的方法包括以下步骤：在操作期间接收用于逻辑的较慢部分的时钟频率测量; 产生本地信号以指示操作的开始并用作时钟选通信号; 将时钟门控信号锁存到选定的周期; 基于时钟门控信号产生时钟域控制，使得操作在所选择的周期上开始生效; 并且在未锁定的锁存器中传播时钟门控信号多个周期，使得第二操作被限制为被启动直到操作完成。

7. 发明授权

US06229754B1 Write through function for a memory 有权
标题翻译：写入内存的功能
公开(公告)号：US06229754B1
公开(公告)日：2001-05-08
申请号：US09501393
申请日：2000-02-09
申请人： Eric Lee Carter , Moon Ho Lee , Michael Richard Ouellette , Geoffrey Wang , Michael Hemsley Wood
发明人： Eric Lee Carter , Moon Ho Lee , Michael Richard Ouellette , Geoffrey Wang , Michael Hemsley Wood
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： A multi-port electronic memory has a write through capability. Control features for enabling a write through path to an output and subsequently disabling without causing data errors due to design and technology variations are provided. Control features are especially beneficial for use with compilable SRAM books.
摘要翻译：多端口电子存储器具有写入功能。提供了用于启用到输出的写入路径并随后禁用而不会由于设计和技术变化而导致数据错误的控制特征。控制功能特别适用于可编译SRAM书籍。

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