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1. 发明授权

US07791126B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07791126B2
公开(公告)日：2010-09-07
申请号：US11615349
申请日：2006-12-22
申请人： Giuseppe Cina , Lorenzo Todaro
发明人： Giuseppe Cina , Lorenzo Todaro
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity comprising a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of equidistantly spaced active areas with the non-volatile memory cells integrated therein, each non-volatile memory cell having a source region, a drain region and a floating gate electrode coupled to a control gate electrode, a group of the memory cells sharing a common source line of a second type of conductivity, an implanted region of said second type of conductivity inside at least one of the plurality of active areas in electric contact with the common source line, and at least one source contact aligned and in electric contact with the implanted region.
摘要翻译：集成在第一类型导电体的半导体衬底上的非易失性存储器件，包括被称为位线的称为字线的行（被称为字线）和列的非易失性存储器单元矩阵，该器件包括多个等距间隔的有源具有集成在其中的非易失性存储单元的区域，每个非易失性存储单元具有耦合到控制栅电极的源极区，漏区和浮栅，一组存储单元共享共同源极线第二类型的导电性，在与公共源极线电接触的多个有源区域中的至少一个中的所述第二导电类型的注入区域以及与所述注入区域对准并电接触的至少一个源极触点。

2. 发明申请

US20070183201A1 NON-VOLATILE MEMORY DEVICE AND MANUFACTURING PROCESS 有权
标题翻译：非易失性存储器件和制造工艺
公开(公告)号：US20070183201A1
公开(公告)日：2007-08-09
申请号：US11615349
申请日：2006-12-22
申请人： Giuseppe Cina , Lorenzo Todaro
发明人： Giuseppe Cina , Lorenzo Todaro
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device integrated on a semiconductor substrate of a first type of conductivity comprising a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of equidistantly spaced active areas with the non-volatile memory cells integrated therein, each non-volatile memory cell having a source region, a drain region and a floating gate electrode coupled to a control gate electrode, a group of the memory cells sharing a common source line of a second type of conductivity, an implanted region of said second type of conductivity inside at least one of the plurality of active areas in electric contact with the common source line, and at least one source contact aligned and in electric contact with the implanted region.
摘要翻译：集成在第一类型导电体的半导体衬底上的非易失性存储器件，包括被称为位线的称为字线的行（被称为字线）和列的非易失性存储器单元矩阵，该器件包括多个等距间隔的有源具有集成在其中的非易失性存储单元的区域，每个非易失性存储单元具有耦合到控制栅电极的源极区，漏区和浮栅，一组存储单元共享共同源极线第二类型的导电性，在与公共源极线电接触的多个有源区域中的至少一个中的所述第二导电类型的注入区域以及与所述注入区域对准并电接触的至少一个源极触点。

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