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    • 1. 发明授权
    • Switching systems and methods using wildcard searching
    • 使用通配符搜索切换系统和方法
    • US07774374B1
    • 2010-08-10
    • US11617716
    • 2006-12-28
    • Govind KizhepatMin H. TengKenneth Y. Y. Choy
    • Govind KizhepatMin H. TengKenneth Y. Y. Choy
    • G06F7/00
    • H04L49/254H04L49/101H04L49/109
    • In some embodiments, a hardware linked-list manager includes a wildcard search controller for generating corresponding queue-specific read requests from wildcard read requests. The linked-list manager may be part of an on-chip interagent switch for allowing a plurality of agents to communicate with each other. The interagent switch may include a crossbar switch and a plurality of hardware linked-list managers integrated on the chip, connected to a random access memory, and connected to the crossbar switch such that the crossbar switch is capable of connecting each of the linked-list managers to each of the agents. Each linked-list manager sends agent-generated data to the memory for storage in the memory as a linked-list element, and retrieves linked-list elements from memory in response to agent read requests. A shared free-memory linked-list manager may maintain a linked list of free memory locations, and provide free memory address locations to a linked list manager upon request.
    • 在一些实施例中,硬件链表管理器包括通配符搜索控制器,用于从通配符读请求生成相应的队列特定读请求。 链表管理器可以是用于允许多个代理相互通信的片上代理交换机的一部分。 间隔开关可以包括交叉开关和集成在芯片上的多个硬件链接列表管理器,连接到随机存取存储器,并且连接到交叉开关,使得交叉开关能够连接每个链表 经理到每个代理商。 每个链表管理器将代理生成的数据发送到存储器,作为链接列表元素存储在存储器中,并响应于代理读取请求从存储器检索链表。 共享的可用内存链接列表管理器可以维护可用存储器位置的链接列表,并且根据请求向链接列表管理器提供可用的存储器地址位置。
    • 3. 发明授权
    • On-chip packet-based interconnections using repeaters/routers
    • 使用中继器/路由器的片上基于分组的互连
    • US07543250B1
    • 2009-06-02
    • US11283210
    • 2005-11-18
    • Govind KizhepatOmar M. Kinaan
    • Govind KizhepatOmar M. Kinaan
    • G06F17/50
    • G06F17/5045G06F17/5077G06F2217/66
    • In some embodiments, multiple functional blocks (agents) in a complex integrated circuit are connected to a physically-distant shared resource (e.g. a memory controller) through packet buses which do not depend on establishing clock-cycle sequenced handshakes. On-chip repeaters including one or more register stages are used to segment the agent-shared resource interconnects into multiple segments, each shorter than a single-clock-cycle pathlength. The interconnects of multiple closely-spaced agents can be routed to the shared resource through an on-chip router having a single routed connection to the shared resource, for reducing the floorplan space taken by interconnects. The packet-based communications protocols do not require redesigning the agents or memory controller to make protocol changes accounting for the clock cycles inserted by repeaters and/or routers. Each agent can include a port register for storing a corresponding port number of the shared resource, to facilitate the host-programmable assignment of agents to shared resource ports.
    • 在一些实施例中,复合集成电路中的多个功能块(代理)通过不依赖于建立时钟周期排序的握手的分组总线连接到物理上远的共享资源(例如,存储器控制器)。 包括一个或多个寄存器级的片上转发器用于将代理共享的资源互连分割成多个段,每个段短于单个时钟周期的路径长度。 多个紧密间隔的代理的互连可以通过具有到共享资源的单个路由连接的片上路由器路由到共享资源,以减少互连所占用的平面布局空间。 基于分组的通信协议不需要重新设计代理或存储器控制器,以便对由中继器和/或路由器插入的时钟周期进行协议改变。 每个代理可以包括用于存储共享资源的对应端口号的端口寄存器,以便于主机可编程地将代理分配给共享资源端口。
    • 4. 发明授权
    • Direct hardware processing of internal data structure fields
    • 直接硬件处理内部数据结构领域
    • US07493481B1
    • 2009-02-17
    • US10848485
    • 2004-05-17
    • Govind KizhepatKenneth Y ChoySuresh Kadiyala
    • Govind KizhepatKenneth Y ChoySuresh Kadiyala
    • G06F9/00G06F7/00
    • G06F9/345G06F9/30018G06F9/30043G06F9/30105G06F9/3012G06F9/3013G06F9/3016
    • In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.
    • 在一些实施例中,通过使用片上模板寄存器和适当的机器码指令来加速对数据结构的内部字段的加载和存储指令的执行。 加载/存储机器代码指令包括相对于数据结构的基址的内部字段的存储器地址偏移的标识符,内部字段的字内起始位的标识符和内部字段的标识符 内部字段的长度。 三个标识符可以重合,例如,如果三个标识符由存储包括存储器地址偏移,开始位置和字段长度的模板条目的模板寄存器的标识表示。 三个标识符也可以作为机器码指令本身的一部分来提供。 进一步提供的是编译器,编译器方法和用于实现加速的内部场负载和存储操作的硬件系统。
    • 7. 发明授权
    • Video transcoder stream multiplexing systems and methods
    • 视频转码器流复用系统和方法
    • US08325821B1
    • 2012-12-04
    • US13369169
    • 2012-02-08
    • Govind KizhepatErik NystromYung-Hsiao Lai
    • Govind KizhepatErik NystromYung-Hsiao Lai
    • H04N7/12H04N11/02H04N11/04H04B1/66
    • H04N21/242H04N19/40H04N21/234345H04N21/23608H04N21/4345
    • In some embodiments, a video (e.g. MPEG-2, H.264) transcoder channel pool is used to transcode multiple independent videos (programs) per channel substantially concurrently. A syntactically-unified combined input video stream is assembled by interleaving segments of different input video streams. The combined stream may be a container stream or elementary stream. Each segment includes one or more groups of pictures (GOP). The combined stream includes the payload video data of the input streams in unmodified form, and modified header data characterizing the combined stream as a single video stream. The combined input stream is transcoded using a single transcoder channel/input port to generate a combined output video stream. Multiple independent output video streams are assembled by de-interleaving segments of the combined output video stream according to stored interleaving break identifiers. Assembling the output video streams includes updating output video stream header fields according to stored header field data.
    • 在一些实施例中,视频(例如,MPEG-2,H.264)代码转换器信道池用于基本同时对每个信道的多个独立视频(节目)进行代码转换。 通过交织不同输入视频流的片段来组合语法统一的组合输入视频流。 组合的流可以是容器流或基本流。 每个片段包括一组或多组照片(GOP)。 组合流包括未修改形式的输入流的有效载荷视频数据和将组合流表征为单个视频流的修改的报头数据。 组合的输入流使用单个代码转换器通道/输入端口进行代码转换以产生组合的输出视频流。 通过根据存储的交织中断标识符对组合输出视频流的段进行解交织来组合多个独立输出视频流。 组合输出视频流包括根据存储的报头字段数据来更新输出视频流报头字段。
    • 10. 发明授权
    • Scalable real-time video compositing systems and methods
    • 可扩展实时视频合成系统和方法
    • US09077578B1
    • 2015-07-07
    • US13154222
    • 2011-06-06
    • Govind KizhepatYung-Hsiao Lai
    • Govind KizhepatYung-Hsiao Lai
    • G06F15/16H04N7/12H04L29/06H04N21/236
    • H04N19/40H04L29/06H04N19/48H04N21/234309H04N21/236H04N21/2365H04N21/25825H04N21/4312
    • In some embodiments, a server system composites in real-time, in response to a user video search query, a standard-compliant (e.g. MPEG-4/H.264) SD or HD video stream encoding a rectangular (x-y) composite video preview panel array (grid) of video search results. Each panel/tile in the rectangular panel array displays a temporal section (e.g. the first 90 seconds, looped-back) of a video identified in response to the user query. Generating the composite video panel array in real-time is achieved by compositing the component video panels in the compressed domain, after each panel undergoes off-line a compressed-domain pre-compositing preparation process that facilitates dynamic compositing of the panels into a single video stream. The pre-compositing preparation includes transcoding to a format having a down-scaled common resolution, common GOP structure, and one-slice-per-row slice structure.
    • 在一些实施例中,响应于用户视频搜索查询,服务器系统实时地复合编码矩形(xy)复合视频预览的标准兼容(例如,MPEG-4 / H.264)SD或HD视频流 视频搜索结果的面板阵列(网格)。 矩形面板阵列中的每个面板/瓦片显示响应于用户查询识别的视频的时间部分(例如,前90秒,回圈)。 通过将压缩域中的分量视频面板合成,每个面板经过离线压缩域预合成准备过程,便于将面板动态合成为单个视频,实现复合视频面板阵列的实时生成 流。 预合成准备包括代码转换为具有缩小的公共分辨率,公共GOP结构和单行片层结构的格式。