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1. 发明授权

US10990556B2 Programmable logic device with on-chip user non-volatile memory 有权
公开(公告)号：US10990556B2
公开(公告)日：2021-04-27
申请号：US14831204
申请日：2015-08-20
申请人： Gowin Semiconductor Corporation, Ltd.
发明人： Jinghui Zhu , San-Ta Kow
IPC分类号： G06F13/40 , G06F13/10 , G06F13/16 , G06F9/445 , G06F15/78 , G06F9/4401
摘要： The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a SRAM array and a logic block array with an interface; the SRAM array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during FPGA's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.

2. 发明授权

US10997088B2 Secrecy system and decryption method of on-chip data stream of nonvolatile FPGA 有权
公开(公告)号：US10997088B2
公开(公告)日：2021-05-04
申请号：US15633172
申请日：2017-06-26
申请人： Gowin Semiconductor Corporation, Ltd
发明人： San-Ta Kow , Jinghui Zhu , Diwakar Chopperla
IPC分类号： G06F21/00 , G06F12/14 , G06F3/06
摘要： A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.

3. 发明申请

US20180011803A1 Secrecy System And Decryption Method Of On-Chip Data Stream Of Nonvolatile FPGA 审中-公开
公开(公告)号：US20180011803A1
公开(公告)日：2018-01-11
申请号：US15633172
申请日：2017-06-26
申请人： Gowin Semiconductor Corporation, Ltd
发明人： San-Ta Kow , Jinghui Zhu , Diwakar Chopperla
IPC分类号： G06F12/14 , G06F3/06
CPC分类号： G06F12/1408 , G06F3/0619 , G06F3/062 , G06F3/0623 , G06F3/0652 , G06F3/0679 , G06F3/0688
摘要： A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.

4. 发明申请

US20190361624A1 DATA PROCESSING METHOD AND DEVICE FOR NONVOLATILE MEMORY AND STORAGE MEDIUM 审中-公开
公开(公告)号：US20190361624A1
公开(公告)日：2019-11-28
申请号：US16028406
申请日：2018-07-05
申请人： Gowin Semiconductor Corporation
发明人： San-Ta Kow , Jinghui Zhu , Diwakar Chopperla
IPC分类号： G06F3/06
摘要： The present disclosure provides a data processing method and a device for a nonvolatile memory and a storage medium. The data processing method comprises: performing a full erase operation on the nonvolatile memory if a full erase operation command is received, such that the nonvolatile memory enters an initial state, wherein the initial state refers to a state in which all operations performed on the nonvolatile memory are valid; in the initial state, storing a data if the data is written in the memory is detected, wherein the data comprises a flag information; detecting the flag information if a data readout command triggered by a user is received; and identifying that the nonvolatile memory is in a default state and prohibiting the user from reading the data stored in the nonvolatile memory if the flag information is detected as an unreadable flag information.

5. 发明申请

US20160274816A1 Programmable Logic Device With On-Chip User Non-Volatile Memory 审中-公开
标题翻译：具有片上用户非易失性存储器的可编程逻辑器件
公开(公告)号：US20160274816A1
公开(公告)日：2016-09-22
申请号：US14831204
申请日：2015-08-20
申请人： Gowin Semiconductor Corporation, Ltd.
发明人： Jinghui Zhu , San-Ta Kow
IPC分类号： G06F3/06 , G06F13/16 , G06F13/40 , G06F13/10
CPC分类号： G06F13/4068 , G06F9/4401 , G06F9/44505 , G06F13/102 , G06F13/1668 , G06F15/7871
摘要： The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a SRAM array and a logic block array with an interface; the SRAM array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during FPGA's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.
摘要翻译：本发明公开了一种具有片上用户非易失性存储器的可编程逻辑器件，包括：可编程逻辑阵列，其是用户可编程逻辑阵列，包括SRAM阵列和具有接口的逻辑块阵列; SRAM阵列用于存储配置数据以实时控制逻辑块阵列，因此可以形成逻辑块以执行用户期望的功能; 非易失性存储块，包括存储配置数据的一个或多个段和存储在配置之后的FPGA正常操作期间使用的用户数据的一个或多个段; 非易失性存储器块仅具有一个接口，并且非易失性存储器块通过接口连接到编程控制器; 编程控制器，其可以通过数据总线，地址总线和相应的控制信号随机访问非易失性存储器。

6. 发明授权

US11157421B2 System level integrated circuit chip 有权
公开(公告)号：US11157421B2
公开(公告)日：2021-10-26
申请号：US15857672
申请日：2017-12-29
申请人： Gowin Semiconductor Corporation
发明人： Jinghui Zhu , San-Ta Kow , Tun Jun Gao , Diwakar Chopperla , Chienkuang Chen , Ning Song
IPC分类号： G06F13/10 , H03K19/177 , G06F12/06 , G06F13/42 , G06F13/12
摘要： The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array. The present application solves the problem of the combination of a variety of different devices and the integration of processing capabilities with different applications.

7. 发明申请

US20190114268A1 SYSTEM LEVEL INTEGRATED CIRCUIT CHIP 审中-公开
公开(公告)号：US20190114268A1
公开(公告)日：2019-04-18
申请号：US15857672
申请日：2017-12-29
申请人： Gowin Semiconductor Corporation
发明人： Jinghui Zhu , San-Ta Kow , Tun Jun Gao , Diwakar Chopperla , Chienkuang Chen , Ning Song
IPC分类号： G06F13/10 , H03K19/177 , G06F13/42 , G06F12/06
摘要： The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array. The present application solves the problem of the combination of a variety of different devices and the integration of processing capabilities with different applications.

8. 发明授权

US10521150B2 Data processing method and device for nonvolatile memory and storage medium 有权
公开(公告)号：US10521150B2
公开(公告)日：2019-12-31
申请号：US16028406
申请日：2018-07-05
申请人： Gowin Semiconductor Corporation
发明人： San-Ta Kow , Jinghui Zhu , Diwakar Chopperla
IPC分类号： G06F3/00 , G06F3/06
摘要： The present disclosure provides a data processing method and a device for a nonvolatile memory and a storage medium. The data processing method comprises: performing a full erase operation on the nonvolatile memory if a full erase operation command is received, such that the nonvolatile memory enters an initial state, wherein the initial state refers to a state in which all operations performed on the nonvolatile memory are valid; in the initial state, storing a data if the data is written in the memory is detected, wherein the data comprises a flag information; detecting the flag information if a data readout command triggered by a user is received; and identifying that the nonvolatile memory is in a default state and prohibiting the user from reading the data stored in the nonvolatile memory if the flag information is detected as an unreadable flag information.

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