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    • 5. 发明申请
    • Structure for Enhancing Reference Return Current Conduction
    • 用于增强参考回归电流传导的结构
    • US20110147068A1
    • 2011-06-23
    • US12641381
    • 2009-12-18
    • Joseph J. CahillAnand HaridassRoger D. Weekly
    • Joseph J. CahillAnand HaridassRoger D. Weekly
    • H05K1/11G06F17/50
    • H05K1/0251G06F17/5077H05K1/162H05K2201/09509H05K2201/09536
    • An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.
    • 提供了一种装置,其包括提供信号路径的多个信令平面和提供电压或接地连接的至少一个内部参考平面。 所述至少一个内部参考平面设置在至少两个信令平面之间。 该装置还包括通过将至少两个信令平面中的第一个信号平面的第一信号平面的信号路径与至少两个信令平面中的第二信号平面的信号路径耦合而进行信号盲/掩蔽。 盲/埋通孔穿过至少一个内部参考平面。 该装置还包括至少两个信令平面中的第一个中的至少一个第一导电特征。 至少一个第一导电特征与信号盲/掩埋通孔紧密接近,并且增加了装置参考平面中电流的电容耦合。
    • 6. 发明授权
    • Off-chip driver circuit with reduced hot-electron degradation
    • 片外驱动电路,减少热电子降解
    • US5726589A
    • 1998-03-10
    • US551663
    • 1995-11-01
    • Joseph J. CahillRobert R. Williams
    • Joseph J. CahillRobert R. Williams
    • H03K19/003H03K19/0185H03K19/0948
    • H03K19/00315
    • An output driver circuit for a semiconductor chip has a push-pull output with a P-channel pull-up and an N-channel pull-down. Predrivers produce push-pull outputs for driving the gates of the output driver. In previous circuits, a stacked arrangement was usually employed where the N-channel pull-down transistor had another N-channel transistor, with gate connected to the voltage supply, in series with it. In this invention, a parallel N-channel or P-channel transistor is employed to shunt part of the current at the beginning of a transition from high-to-low at the output node of the off-chip driver circuit, and thus lower the voltage across the pull-down transistor to a level which will avoid hot-electron degradation. This parallel transistor is small compared to the main N-channel pull-down, and serves to reduce the output node voltage to a level which does not present a likelihood of hot-electron effects in the main pull-down device. Thus, large current flow through the N-channel pull-down is delayed until the voltage is reduced to an acceptable level. At the same time, this delay is not such as would unduly compromise the high speed nature of the circuits.
    • 用于半导体芯片的输出驱动器电路具有P沟道上拉和N沟道下拉的推挽输出。 预驱动器产生用于驱动输出驱动器的门的推挽输出。 在以前的电路中,通常采用堆叠布置,其中N沟道下拉晶体管具有另一个N沟道晶体管,其栅极连接到电压源,与其串联。 在本发明中,并行N沟道或P沟道晶体管用于在片外驱动电路的输出节点从高到低的转变开始时分流电流的一部分,从而降低 跨越下拉晶体管的电压达到避免热电子降解的水平。 该并联晶体管与主N沟道下拉相比较小,并且用于将输出节点电压降低到在主下拉器件中不存在热电子效应的可能性的水平。 因此,延迟通过N沟道下拉的大电流流动直到电压降低到可接受的水平。 同时,这种延迟不是会不利地影响电路的高速性质。
    • 9. 发明授权
    • Structure for enhancing reference return current conduction
    • 用于增强参考回流导通的结构
    • US08295058B2
    • 2012-10-23
    • US12641381
    • 2009-12-18
    • Joseph J. CahillAnand HaridassRoger D. Weekly
    • Joseph J. CahillAnand HaridassRoger D. Weekly
    • H05K1/11H05K7/14H05K9/00
    • H05K1/0251G06F17/5077H05K1/162H05K2201/09509H05K2201/09536
    • An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.
    • 提供了一种装置,其包括提供信号路径的多个信令平面和提供电压或接地连接的至少一个内部参考平面。 所述至少一个内部参考平面设置在至少两个信令平面之间。 该装置还包括通过将至少两个信令平面中的第一个信号平面的第一信号平面的信号路径与至少两个信令平面中的第二信号平面的信号路径耦合而进行信号盲/掩蔽。 盲/埋通孔穿过至少一个内部参考平面。 该装置还包括至少两个信令平面中的第一个中的至少一个第一导电特征。 至少一个第一导电特征与信号盲/掩埋通孔紧密接近,并且增加了装置参考平面中电流的电容耦合。