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1. 发明申请

US20100006904A1 Apparatus and Method for Input/Output Module That Optimizes Frequency Performance in a Circuit 有权
标题翻译：用于优化电路中频率性能的输入/输出模块的装置和方法
公开(公告)号：US20100006904A1
公开(公告)日：2010-01-14
申请号：US12172247
申请日：2008-07-13
申请人： Guu Lin , Yen-Fu Lin , Stephanie T. Tran , Pooyan Khoshkhoo
发明人： Guu Lin , Yen-Fu Lin , Stephanie T. Tran , Pooyan Khoshkhoo
IPC分类号： H01L27/10 , H01L21/44
CPC分类号： H01L23/5382 , H01L23/50 , H01L24/06 , H01L2224/0401 , H01L2224/05553 , H01L2224/81801 , H01L2924/01004 , H01L2924/01033 , H01L2924/01075 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/3025 , H03K19/0175
摘要： A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having signal pads that are configurable to route varying signals between the circuit and at least one external device. The module can also have voltage pads that are configurable to route substantially constant voltages between at least one external device and the circuit. The signal pads can be interleaved between the voltage pads. A module with one or more of these features can achieve ideal performance in both wire bond and flip chip packages with the flexibility of setting a different input/output utilization percentage within the module.
摘要翻译：电路可以包括具有可配置为在电路和至少一个外部设备之间路由信号的信号焊盘的模块。模块还可以具有在信号焊盘之间交错的未使用的焊盘。电路可以包括具有可配置为在电路和至少一个外部设备之间路由变化的信号的信号焊盘的模块。该模块还可以具有可配置成在至少一个外部设备和电路之间路由基本上恒定的电压的电压焊盘。信号焊盘可以在电压焊盘之间交错。具有一个或多个这些特征的模块可以在引线键合和倒装芯片封装中实现理想的性能，具有在模块内设置不同的输入/输出利用率的灵活性。

2. 发明授权

US08138787B2 Apparatus and method for input/output module that optimizes frequency performance in a circuit 有权
标题翻译：用于输入/输出模块的装置和方法，其优化电路中的频率性能
公开(公告)号：US08138787B2
公开(公告)日：2012-03-20
申请号：US12172247
申请日：2008-07-13
申请人： Guu Lin , Yen-Fu Lin , Stephanie T. Tran , Pooyan Khoshkhoo
发明人： Guu Lin , Yen-Fu Lin , Stephanie T. Tran , Pooyan Khoshkhoo
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H01L23/5382 , H01L23/50 , H01L24/06 , H01L2224/0401 , H01L2224/05553 , H01L2224/81801 , H01L2924/01004 , H01L2924/01033 , H01L2924/01075 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/3025 , H03K19/0175
摘要： A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having signal pads that are configurable to route varying signals between the circuit and at least one external device. The module can also have voltage pads that are configurable to route substantially constant voltages between at least one external device and the circuit. The signal pads can be interleaved between the voltage pads. A module with one or more of these features can achieve ideal performance in both wire bond and flip chip packages with the flexibility of setting a different input/output utilization percentage within the module.
摘要翻译：电路可以包括具有可配置为在电路和至少一个外部设备之间路由信号的信号焊盘的模块。模块还可以具有在信号焊盘之间交错的未使用的焊盘。电路可以包括具有可配置为在电路和至少一个外部设备之间路由变化的信号的信号焊盘的模块。该模块还可以具有可配置成在至少一个外部设备和电路之间路由基本上恒定的电压的电压焊盘。信号焊盘可以在电压焊盘之间交错。具有一个或多个这些特征的模块可以在引线键合和倒装芯片封装中实现理想的性能，具有在模块内设置不同的输入/输出利用率的灵活性。

3. 发明授权

US07317644B1 Signal timing for I/O 有权
标题翻译： I / O信号时序
公开(公告)号：US07317644B1
公开(公告)日：2008-01-08
申请号：US11303250
申请日：2005-12-15
申请人： Guu Lin , Stephanie T. Tran , Yen-Fu Lin
发明人： Guu Lin , Stephanie T. Tran , Yen-Fu Lin
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093
摘要： Circuits, methods, and apparatus for ordering the timing of clock and data signals. Programmable delay cells are utilized in a data output cell to control a critical multiple data rate input/output write timing so the output can achieve better performance, such as higher maximum frequency of output (Fmax) performance. The delay cells ensure that critical timing criteria between clock signals and data high and low signals are satisfied so that there is a reduced chance of output glitching.
摘要翻译：用于排序时钟和数据信号时序的电路，方法和装置。可编程延迟单元用于数据输出单元，以控制关键的多数据速率输入/输出写时序，以便输出可以实现更好的性能，例如更高的最大输出频率（Fmax）性能。延迟单元确保了时钟信号和数据高和低信号之间的关键时序标准得到满足，从而减少了输出毛刺的几率。

4. 发明授权

US08385142B1 Flexible data strobe signal bus structure for wirebond and flip-chip packaging 有权
标题翻译：灵活的数据选通信号总线结构，用于引线键合和倒装芯片封装
公开(公告)号：US08385142B1
公开(公告)日：2013-02-26
申请号：US12464783
申请日：2009-05-12
申请人： Guu Lin , Yen-Fu Lin , Mark W. Fiester , Stephanie T. Tran
发明人： Guu Lin , Yen-Fu Lin , Mark W. Fiester , Stephanie T. Tran
IPC分类号： G11C5/06
CPC分类号： G06F17/5054 , H01L2224/48091 , H01L2924/00014
摘要： An integrated circuit with a flexible data strobe signal (DQS) bus structure is presented. The integrated circuit has a number of input/output (I/O) modules with a number of data pins to receive and transmit data. In addition, a subset of the I/O modules also have a data strobe pin. The input/output modules are connected to data strobe signal buses having a fixed configuration. The configuration of the fixed DQS bus groups a number of data pins with a corresponding data strobe pin and the grouping of data pin spans multiple I/O modules. The integrated circuit also has a flexible data bus connected to the I/O modules. Data pins of I/O modules of a second integrated circuit are mapped a subset of the data pins of corresponding I/O modules of the integrated circuit. The flexible data strobe signal bus enables selection of the subset of data pins in the integrated circuit.
摘要翻译：提出了一种具有灵活数据选通信号（DQS）总线结构的集成电路。集成电路具有多个具有多个数据引脚的输入/输出（I / O）模块，用于接收和发送数据。此外，I / O模块的一个子集还具有一个数据选通引脚。输入/输出模块连接到具有固定配置的数据选通信号总线。固定DQS总线的配置将多个具有相应数据选通引脚的数据引脚组合在一起，数据引脚分组跨多个I / O模块。集成电路还具有连接到I / O模块的灵活数据总线。将第二集成电路的I / O模块的数据引脚映射到集成电路的相应I / O模块的数据引脚的子集。灵活的数据选通信号总线使得能够选择集成电路中的数据引脚子集。

5. 发明授权

US07250660B1 ESD protection that supports LVDS and OCT 有权
标题翻译：支持LVDS和OCT的ESD保护
公开(公告)号：US07250660B1
公开(公告)日：2007-07-31
申请号：US10891988
申请日：2004-07-14
申请人： Cheng-Hsiung Huang , Chih-Ching Shih , Jeffrey Tyhach , Guu Lin , Chiakang Sung , Stephanie T. Tran
发明人： Cheng-Hsiung Huang , Chih-Ching Shih , Jeffrey Tyhach , Guu Lin , Chiakang Sung , Stephanie T. Tran
IPC分类号： H01L23/62 , H01L29/72 , H01L29/73 , H01L29/74 , H01L31/111
CPC分类号： H01L27/0266
摘要： Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.
摘要翻译：描述了为支持低电压差分信号（LVDS）和片上终止（OCT）标准的I / O电路提供静电放电保护的电路。在I / O晶体管上连接至少一个附加晶体管。在LVDS的情况下，使用一对堆叠的晶体管，其中源/漏区和阱抽头之间的距离对于连接到I / O焊盘的晶体管相当大。 PMOS晶体管和NMOS晶体管也可以串联连接在诸如电源节点的第一节点和I / O焊盘之间。还公开了一种OCT电路，其中源极/漏极区域和OCT晶体管中的阱阱之间的间隔小于I / O晶体管中的间距。

6. 发明授权

US07271989B2 Electrostatic discharge protection circuit 有权
公开(公告)号：US07271989B2
公开(公告)日：2007-09-18
申请号：US10861604
申请日：2004-06-03
申请人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin S. Lee , Chih-Ching Shih , Irfan Rahim , Stephanie T. Tran
发明人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin S. Lee , Chih-Ching Shih , Irfan Rahim , Stephanie T. Tran
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L27/0251
摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

7. 发明授权

US07400480B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US07400480B2
公开(公告)日：2008-07-15
申请号：US11890933
申请日：2007-08-07
申请人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin S. Lee , Chih-Ching Shih , Irfan Rahim , Stephanie T. Tran
发明人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin S. Lee , Chih-Ching Shih , Irfan Rahim , Stephanie T. Tran
IPC分类号： H02H3/22
CPC分类号： H01L27/0266 , H01L27/0251
摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.
摘要翻译：提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

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