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    • 1. 发明申请
    • ECC Encoder Using Partial-Parity Feedback
    • ECC编码器采用部分奇偶校验反馈
    • US20150363263A1
    • 2015-12-17
    • US14303393
    • 2014-06-12
    • HGST Netherlands B.V.
    • Martin Aureliano HassnerKirk Hwang
    • G06F11/10H03M13/11
    • H03M13/1134H03M13/152H03M13/1595H03M13/6575
    • ECC Encoders that process packets of p bits (with p>1) in a data block in parallel and generate a set of N parity/check bits that are stored along with the original data in the memory block. Encoders according to the invention can be used to create a nonvolatile NAND Flash memory write cache with BCH-ECC for use in a disk drive that can speed up the response time for some write operations. Encoder embodiments of the invention use Partial-Parity Feedback along with a XOR-Matrix Logic Module, which calculates N output bits from p input bits, and a Shift Register Module that accumulates N check bits. The XOR-Matrix Logic Module is designed using a precalculated Matrix of p×N bits, which is translated into VHDL design language to generate the hardware gates. High-Order p-bit Partial-Parity Feedback improves over LFSR designs and achieves Minimal Critical Path Length:=p.
    • ECC编码器并行处理数据块中p位(p> 1)的数据包,并生成与原始数据一起存储在存储器块中的一组N个奇偶校验/校验位。 根据本发明的编码器可用于创建具有用于磁盘驱动器的BCH-ECC的非易失性NAND闪存写入高速缓存,其可以加速某些写入操作的响应时间。 本发明的编码器实施例使用部分奇偶校验反馈以及从P个输入位计算N个输出位的XOR矩阵逻辑模块和累积N个校验位的移位寄存器模块。 XOR矩阵逻辑模块使用预先计算的p×N位矩阵进行设计,将其转换为VHDL设计语言以生成硬件门。 高阶p位部分奇偶校验反馈改进了LFSR设计,实现了最小临界路径长度:= p。