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1. 发明授权

US09614050B2 Method for manufacturing semiconductor devices 有权
公开(公告)号：US09614050B2
公开(公告)日：2017-04-04
申请号：US14414355
申请日：2012-08-06
申请人： Haizhou Yin , Keke Zhang
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L21/337 , H01L29/66 , H01L21/768 , H01L21/285
CPC分类号： H01L29/66492 , H01L21/28518 , H01L21/76897 , H01L29/66583 , H01L29/6659
摘要： The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover source and drain regions and expose a gate region; forming an interlayer dielectric layer on the substrate to cover the contact sacrificial pattern and expose the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern to form the source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of a contact sacrificial layer process, the method of manufacturing a semiconductor device according to the present invention effectively reduces the distance between the gate spacer and the contact region and increases the area of the contact region, thus effectively reducing the parasitic resistance of the device.

2. 发明授权

US09576802B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09576802B2
公开(公告)日：2017-02-21
申请号：US14412173
申请日：2012-07-19
申请人： Haizhou Yin , Huilong Zhu , Keke Zhang
发明人： Haizhou Yin , Huilong Zhu , Keke Zhang
IPC分类号： H01L21/331 , H01L21/28 , H01L29/66 , H01L21/3105 , H01L29/78 , H01L29/423 , H01L29/417
CPC分类号： H01L21/28114 , H01L21/28088 , H01L21/31051 , H01L29/41783 , H01L29/42376 , H01L29/4966 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/78 , H01L29/7834
摘要： A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括：在衬底上形成T形虚拟栅极结构; 去除T形虚拟栅极结构并保持T形栅极沟槽; 通过在T形栅极沟槽中填充金属层来形成T形金属栅极结构。根据本申请中公开的半导体器件制造方法，通过形成T形虚拟栅极和T形栅极沟槽，在随后的金属栅极填充处理中避免了突出现象和空隙的形成，并且器件性能改进了

3. 发明授权

US09530861B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09530861B2
公开(公告)日：2016-12-27
申请号：US14399260
申请日：2012-07-03
申请人： Haizhou Yin , Keke Zhang
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L29/66 , H01L29/78 , H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L29/66545 , H01L21/28008 , H01L29/4966 , H01L29/517 , H01L29/7833
摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a dummy gate stack structure on a substrate, wherein the dummy gate stack structure contains carbon-based materials; forming source/drain region in the substrate on both sides of the dummy gate stack structure; performing etching to remove the dummy gate stack structure until the substrate is exposed, resulting in a gate trench; and forming a gate stack structure in the gate trench. In accordance with the method for manufacturing a semiconductor device of the present invention, the dummy gate made of carbon-based materials is used to substitute the dummy gate made of silicon-based materials, then no oxide liner and/or etch blocking layer needs be added while the dummy gate is removed by etching in the gate last process, thus the reliability of device is ensured while the process is simplified and the cost is reduced.
摘要翻译：本发明公开了一种制造半导体器件的方法，包括以下步骤：在衬底上形成虚拟栅叠层结构，其中虚栅极堆叠结构包含碳基材料; 在所述虚拟栅极堆叠结构的两侧上的所述衬底中形成源极/漏极区域; 执行蚀刻以去除伪栅极堆叠结构，直到基板被暴露，产生栅极沟槽; 以及在栅极沟槽中形成栅叠层结构。根据本发明的半导体器件的制造方法，使用由碳基材料制成的虚拟栅极来代替由硅基材料制成的虚拟栅极，然后不需要氧化物衬底和/或蚀刻阻挡层通过栅极最后工艺中的蚀刻去除伪栅极，从而确保了器件的可靠性，同时简化了工艺并降低了成本。

4. 发明申请

US20150200269A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150200269A1
公开(公告)日：2015-07-16
申请号：US14414355
申请日：2012-08-06
申请人： Haizhou Yin , Keke Zhang
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L29/66 , H01L21/285
CPC分类号： H01L29/66492 , H01L21/28518 , H01L21/76897 , H01L29/66583 , H01L29/6659
摘要： The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover source and drain regions and expose a gate region; forming an interlayer dielectric layer on the substrate to cover the contact sacrificial pattern and expose the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern to form the source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of a contact sacrificial layer process, the method of manufacturing a semiconductor device according to the present invention effectively reduces the distance between the gate spacer and the contact region and increases the area of the contact region, thus effectively reducing the parasitic resistance of the device.
摘要翻译：本发明提供一种制造半导体器件的方法，包括：在衬底上形成接触牺牲图案以覆盖源极和漏极区域并露出栅极区域; 在所述衬底上形成层间电介质层以覆盖所述接触牺牲图案并露出所述栅极区域; 在所述暴露的栅极区域中形成栅极堆叠结构; 去除接触牺牲图案以形成源极/漏极接触沟槽; 以及在源极/漏极接触沟槽中形成源极/漏极接触。通过接触牺牲层工艺，根据本发明的制造半导体器件的方法有效地减小了栅极间隔物和接触区域之间的距离，并且增加了接触区域的面积，从而有效地降低了接触区域的寄生电阻设备。

5. 发明申请

US20130299920A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130299920A1
公开(公告)日：2013-11-14
申请号：US13698284
申请日：2012-07-03
申请人： Haizhou Yin , Keke Zhang
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L29/4966 , H01L29/517 , H01L29/66477 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： The present invention discloses a semiconductor device, comprising a substrate, a gate stack structure on the substrate, a gate spacer structure at both sides of the gate stack structure, source/drain regions in the substrate and at opposite sides of the gate stack structure and the gate spacer structure, characterized in that the gate spacer structure comprises at least one gate spacer void filled with air. In accordance with the semiconductor device and the method for manufacturing the same of the present invention, carbon-based materials are used to form a sacrificial spacer, and at least one air void is formed after removing the sacrificial spacer, the overall dielectric constant of the spacer is effectively reduced. Thus, the gate parasitic capacitance is reduced and the device performance is enhanced.
摘要翻译：本发明公开了一种半导体器件，包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构两侧的栅极间隔结构，衬底中的源极/漏极区域和栅极堆叠结构的相对侧，以及门间隔结构，其特征在于栅极间隔结构包括填充有空气的至少一个栅极间隔物空隙。根据本发明的半导体器件及其制造方法，使用碳基材料来形成牺牲隔离物，并且在去除牺牲间隔物之后形成至少一个空气孔，其中介电常数间隔物有效减少。因此，栅极寄生电容减小，器件性能提高。

6. 发明申请

US20150194501A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20150194501A1
公开(公告)日：2015-07-09
申请号：US14413616
申请日：2012-08-03
申请人： Haizhou Yin , Keke Zhang
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L29/66
CPC分类号： H01L29/6659 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method for manufacturing a semiconductor device, comprising: forming a gate stack structure and gate spacers on the substrate; forming the raised S/D regions on the substrate on both sides of the gate stack structure and the gate spacers; depositing a lower interlayer dielectric layer on the entire device, and planarizing the lower interlayer dielectric layer and the gate stack structure until the raised S/D regions are exposed; selective epitaxial growing to form the S/D extension regions in the raised S/D regions; forming an upper interlayer dielectric layer on the S/D extension regions; etching the upper interlayer dielectric layer until the S/D extension regions to form an S/D contact hole; forming a metal silicide in the S/D contact hole.
摘要翻译：一种制造半导体器件的方法，包括：在所述衬底上形成栅叠层结构和栅间隔; 在栅极叠层结构和栅极间隔物两侧的基板上形成凸起的S / D区域; 在整个器件上沉积下层间介质层，并平坦化下层间介质层和栅叠层结构，直到凸起的S / D区域露出; 选择性外延生长以在凸起的S / D区域中形成S / D延伸区域; 在S / D延伸区上形成上层间介电层; 蚀刻上层间介电层，直到S / D延伸区域形成S / D接触孔; 在S / D接触孔中形成金属硅化物。

7. 发明申请

US20150214097A1 METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION 审中-公开
标题翻译：制造浅层分离分离方法
公开(公告)号：US20150214097A1
公开(公告)日：2015-07-30
申请号：US14413966
申请日：2012-08-03
申请人： Haizhou Yin , Keke Zhang
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L21/762 , H01L21/3065 , H01L29/06 , H01L21/3105 , H01L21/02 , H01L21/306 , H01L21/308
CPC分类号： H01L21/76229 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/30604 , H01L21/3065 , H01L21/3081 , H01L21/3083 , H01L21/31053 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/0649 , H01L29/7846
摘要： The present invention provides a method for manufacturing a shallow trench isolation, comprising: forming a hard mask layer on the substrate; phottoetching/etching the hard mask layer and the substrate to form a plurality of first trenches along a first direction and a plurality of second trenches along a second direction perpendicular to the first direction, wherein the volume of the second trench is greater than that of the first trench; depositing an insulating material in the first and second trenches; planarizing the insulating material and the hard mask layer until the substrate is exposed so as to form a shallow trench isolation. According to a method of the present invention, the shallow trench isolation is allowed by etch-filling to be deep and wide in the channel width direction and shallow and narrow in the channel length direction, and stress is applied to NMOS and PMOS simultaneously to increase the carrier mobility of the channel region, thereby improving the overall driving capability of the device.
摘要翻译：本发明提供一种用于制造浅沟槽隔离的方法，包括：在所述衬底上形成硬掩模层; 蚀刻/蚀刻硬掩模层和基板以沿着垂直于第一方向的第二方向沿着第一方向和多个第二沟槽形成多个第一沟槽，其中第二沟槽的体积大于第一沟在第一和第二沟槽中沉积绝缘材料; 平面化绝缘材料和硬掩模层直到基板被暴露以便形成浅沟槽隔离。根据本发明的方法，通过蚀刻填充允许浅沟槽隔离在沟道宽度方向上深而宽，并且在沟道长度方向上浅和窄，并且同时施加应力到NMOS和PMOS以增加通道区域的载流子迁移率，从而提高装置的整体驱动能力。

8. 发明申请

US20150118818A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150118818A1
公开(公告)日：2015-04-30
申请号：US14399260
申请日：2012-07-03
申请人： Haizhou Yin , Keke Zhang
发明人： Haizhou Yin , Keke Zhang
IPC分类号： H01L29/66 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28008 , H01L29/4966 , H01L29/517 , H01L29/7833
摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a dummy gate stack structure on a substrate, wherein the dummy gate stack structure contains carbon-based materials; forming source/drain region in the substrate on both sides of the dummy gate stack structure; performing etching to remove the dummy gate stack structure until the substrate is exposed, resulting in a gate trench; and forming a gate stack structure in the gate trench. In accordance with the method for manufacturing a semiconductor device of the present invention, the dummy gate made of carbon-based materials is used to substitute the dummy gate made of silicon-based materials, then no oxide liner and/or etch blocking layer needs be added while the dummy gate is removed by etching in the gate last process, thus the reliability of device is ensured while the process is simplified and the cost is reduced.
摘要翻译：本发明公开了一种制造半导体器件的方法，包括以下步骤：在衬底上形成虚拟栅叠层结构，其中虚栅极堆叠结构包含碳基材料; 在所述虚拟栅极堆叠结构的两侧上的所述衬底中形成源极/漏极区域; 执行蚀刻以去除伪栅极堆叠结构，直到基板被暴露，产生栅极沟槽; 以及在栅极沟槽中形成栅叠层结构。根据本发明的半导体器件的制造方法，使用由碳基材料制成的虚拟栅极来代替由硅基材料制成的虚拟栅极，然后不需要氧化物衬底和/或蚀刻阻挡层通过栅极最后工艺中的蚀刻去除伪栅极，从而确保了器件的可靠性，同时简化了工艺并降低了成本。

9. 发明申请

US20140361353A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140361353A1
公开(公告)日：2014-12-11
申请号：US14357572
申请日：2012-07-18
申请人： Haizhou Yin , Huilong Zhu , Keke Zhang
发明人： Haizhou Yin , Huilong Zhu , Keke Zhang
IPC分类号： H01L29/66 , H01L29/423 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28114 , H01L29/1083 , H01L29/42376 , H01L29/66492 , H01L29/778 , H01L29/7833
摘要： The present application discloses a method for manufacturing a semiconductor device, comprising: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; filling successively a gate insulation layer and a metal layer in the T-shape gate trench, wherein the metal layer forms the T-shape metal gate structure. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.
摘要翻译：本申请公开了一种用于制造半导体器件的方法，包括：在所述衬底上形成T形虚拟栅极结构; 去除T形虚拟栅极结构并保持T形栅极沟槽; 在T形栅极沟槽中依次填充栅极绝缘层和金属层，其中金属层形成T形金属栅极结构。根据本申请中公开的半导体器件制造方法，通过形成T形虚拟栅极和T形栅极沟槽，在随后的金属栅极填充处理中避免了突出现象和空隙的形成，并且器件性能改进了

10. 发明授权

US09356025B2 Enhancing MOSFET performance with corner stresses of STI 有权
标题翻译：通过STI拐角应力增强MOSFET性能
公开(公告)号：US09356025B2
公开(公告)日：2016-05-31
申请号：US14348579
申请日：2012-03-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/762 , H01L29/66
CPC分类号： H01L27/092 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/7846
摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.
摘要翻译：本发明涉及利用STI的拐角应力来增强MOSFET的性能。一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准地区。

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