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1. 发明授权

US09696922B2 Storage system 有权
公开(公告)号：US09696922B2
公开(公告)日：2017-07-04
申请号：US14762039
申请日：2013-12-24
申请人： Hitachi, Ltd.
发明人： Naoya Okada , Yusuke Nonaka , Akihiko Araki , Shintaro Kudo , Makio Mizuno
IPC分类号： G06F12/08 , G06F3/06 , G06F12/0875 , G06F12/06 , G06F12/0868 , G06F12/0893
CPC分类号： G06F3/0619 , G06F3/0647 , G06F3/0659 , G06F3/0688 , G06F3/0689 , G06F12/0638 , G06F12/08 , G06F12/0868 , G06F12/0875 , G06F12/0893 , G06F2212/222 , G06F2212/2228 , Y02D10/13
摘要： A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.

2. 发明授权

US09117724B2 Solid-state image sensing device 有权
标题翻译：固态摄像装置
公开(公告)号：US09117724B2
公开(公告)日：2015-08-25
申请号：US14662413
申请日：2015-03-19
申请人： Hitachi, Ltd.
发明人： Tomoyasu Furukawa , Tomohiro Saito , Yusuke Nonaka
IPC分类号： H01L27/146 , H01L29/78
CPC分类号： H01L27/14643 , H01L27/14603 , H01L27/14609 , H01L29/7816 , H04N5/3559 , H04N5/361 , H04N5/374 , H04N5/37452
摘要： A solid-state image sensing device is configured such that a first voltage is applied to a first conductivity type semiconductor region and a second voltage is applied to source-drain regions having a second conductivity type of the MOS capacitance to apply inverse bias between the semiconductor region and the source-drain regions of the MOS capacitance.
摘要翻译：固态图像感测装置被配置为使得第一电压被施加到第一导电类型半导体区域，并且第二电压被施加到具有第二导电类型的MOS电容的源极 - 漏极区域，以在半导体区域和MOS电容的源极 - 漏极区域。

3. 发明申请

US20140281244A1 STORAGE APPARATUS AND CONTROL METHOD FOR STORAGE APPARATUS 有权
标题翻译：存储设备的存储设备和控制方法
公开(公告)号：US20140281244A1
公开(公告)日：2014-09-18
申请号：US13701656
申请日：2012-11-14
申请人： HITACHI, LTD.
发明人： Shintaro Kudo , Yusuke Nonaka , Masanori Takada
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0626 , G06F3/0659 , G06F3/067 , G06F12/0813 , G06F12/0868 , G06F12/0871 , G06F2212/222 , G06F2212/282 , G06F2212/461 , G06F2212/463
摘要： An exemplary storage apparatus of the invention includes storage devices for storing data of block I/O commands and file I/O commands and a controller including a block cache area and a file cache area. The controller creates block I/O commands from file I/O commands and accesses the storage devices in accordance with the created block I/O commands. In a case where the file cache area is lacking an area to cache first data of a received first file I/O command, the controller chooses one of a first cache method that newly creates a free area in the file cache area to cache the first data in the file cache area and a second cache method that caches the first data in the block cache area without caching the first data in the file cache area.
摘要翻译：本发明的示例性存储装置包括用于存储块I / O命令和文件I / O命令的数据的存储装置和包括块高速缓存区域和文件高速缓存区域的控制器。控制器从文件I / O命令创建块I / O命令，并根据创建的块I / O命令访问存储设备。在文件缓存区域缺少高速缓存接收到的第一文件I / O命令的第一数据的区域的情况下，控制器选择在文件高速缓存区域中新创建空闲区域的第一高速缓存方法之一，以缓存第一文件I / 文件高速缓存区域中的数据和缓存第一数据在块高速缓存区域中而不缓存文件高速缓存区域中的第一数据的第二高速缓存方法。

4. 发明授权

US08799580B2 Storage apparatus and data processing method 有权
标题翻译：存储设备和数据处理方法
公开(公告)号：US08799580B2
公开(公告)日：2014-08-05
申请号：US13643440
申请日：2012-10-11
申请人： Hitachi, Ltd.
发明人： Yuki Sakashita , Yusuke Nonaka , Shintaro Kudo
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0862 , G06F3/061 , G06F3/065 , G06F3/0689 , G06F12/0802 , G06F12/0866 , G06F12/0888 , G06F12/126 , G06F2212/601
摘要： To raise the CPU cache hit rate and improve the I/O processing. Controller is CPU configured from a CPU core and a CPU cache wherein the CPU selects memory bus optimization execution processing or cache poisoning optimization execution processing according to an attribute of the access target volume on the basis of an access request. If the memory bus optimization execution processing is selected, CPU loads the target data into the CPU core after storing the target data in the main storage area, and if the cache poisoning optimization execution processing is selected, the CPU loads the target data into the CPU core after storing the target data in the temporary area of the CPU cache from the CPU memory, and the CPU core checks the target data which was loaded from the main storage area or the temporary area of the CPU cache.
摘要翻译：提高CPU缓存命中率，改善I / O处理。控制器是由CPU核心和CPU高速缓存组成的CPU，其中CPU基于访问请求，根据访问目标卷的属性来选择存储器总线优化执行处理或高速缓存中毒优化执行处理。如果选择了存储器总线优化执行处理，则CPU将目标数据存储在主存储区域之后，将目标数据加载到CPU内核中，并且如果选择了高速缓存中毒优化执行处理，则CPU将目标数据加载到CPU 将目标数据从CPU存储器存储在CPU高速缓存的临时区域中，并且CPU核心检查从主存储区域或CPU高速缓存的临时区域加载的目标数据。

5. 发明授权

US10353613B2 Computer system and control method therefor for handling path failure 有权
公开(公告)号：US10353613B2
公开(公告)日：2019-07-16
申请号：US15506967
申请日：2014-11-12
申请人： Hitachi, Ltd.
发明人： Akihiko Araki , Yusuke Nonaka , Masanori Takada , Naoya Okada
IPC分类号： G06F11/00 , G06F3/06 , G06F11/20
摘要： When mounting hardware which is coupled to another portion by a plurality of paths with different applications, despite the hardware being a single device, and a failure occurs in any of the paths, there is a risk that the failure may propagate to other components unless the other paths are also blocked.In order to solve the problem described above, in a storage apparatus to which a device coupled by a plurality of coupling paths with different applications can be mounted, the present invention determines a block range at the time of an occurrence of a failure to be a device and a plurality of coupling paths coupled to the device, manages the block range, and upon an occurrence of a failure, executes failure handling which involves blocking an appropriate block range determined in advance by referring to the information.

6. 发明授权

US10067882B2 Storage system and storage control method 有权
公开(公告)号：US10067882B2
公开(公告)日：2018-09-04
申请号：US15540681
申请日：2015-01-13
申请人： Hitachi, Ltd.
发明人： Miho Imazaki , Akira Yamamoto , Yusuke Nonaka , Tomohiro Yoshihara , Shunji Kawamura
IPC分类号： G06F11/10 , G06F12/109
摘要： A storage system manages correspondence relationships between physical addresses and logical addresses inside a storage device, as well as logical spaces provided by a plurality of storage devices, and when a determination is made as to whether first data and second data are stored in the same storage device in a case in which the first data and the second data are exchanged inside a logical space, and the determination is found to be affirmative, the storage device replaces the logical address corresponding to the first data with the logical address corresponding to the second data without changing the physical address of the physical area in which the first data is stored and the physical address of the physical area in which the second data is stored.

7. 发明授权

US09535864B2 Computer system and control method thereof 有权
标题翻译：计算机系统及其控制方法
公开(公告)号：US09535864B2
公开(公告)日：2017-01-03
申请号：US14632043
申请日：2015-02-26
申请人： Hitachi, Ltd.
发明人： Shintaro Kudo , Yusuke Nonaka
IPC分类号： G06F3/00 , G06F5/00 , G06F13/34 , G06F3/06 , G06F13/16
CPC分类号： G06F13/34 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F3/067 , G06F13/1642
摘要： The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.
摘要翻译：本发明是一种集群存储系统，即使当从一个控制器的处理器发送对另一控制器的处理器的访问时，第二控制器的处理器能够对该访问的处理进行优先级处理，以便I / O处理是也阻止了延迟。利用本发明的存储系统，第一控制器的第一处理器通过区分由第二控制器的第二处理器处理的请求信息来区分待优先处理的请求信息，第二处理器和处理不优先的请求信息，并且第二处理器通过区分要优先处理的请求信息和不优先处理的请求信息来获取请求信息。

8. 发明申请

US20150026395A1 STORAGE SYSTEM AND MANAGEMENT METHOD OF CONTROL INFORMATION THEREIN 审中-公开
标题翻译：存储系统及其控制信息管理方法
公开(公告)号：US20150026395A1
公开(公告)日：2015-01-22
申请号：US14507197
申请日：2014-10-06
申请人： Hitachi, Ltd.
发明人： Akihiko ARAKI , Yusuke Nonaka
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0871 , G06F12/0246 , G06F12/0873 , G06F12/121 , G06F2212/1021 , G06F2212/222 , G06F2212/262 , G06F2212/282 , G06F2212/466 , G06F2212/7208
摘要： An embodiment of this invention divides a cache memory of a storage system into a plurality of partitions and information in one or more of the partitions is composed of data different from user data and including control information. The storage system dynamically swaps data between an LU storing control information and a cache partition. Through this configuration, in a storage system having an upper limit in the capacity of the cache memory, a large amount of control information can be used while access performance to control information is kept.
摘要翻译：本发明的一个实施例将存储系统的高速缓冲存储器划分为多个分区，并且一个或多个分区中的信息由与用户数据不同的数据组成并且包括控制信息。存储系统在LU存储控制信息和高速缓存分区之间动态地交换数据。通过这种配置，在具有高速缓冲存储器的容量上限的存储系统中，可以使用大量的控制信息，同时保持对控制信息的访问性能。

9. 发明申请

US20130215308A1 SOLID-STATE IMAGE SENSING DEVICE 审中-公开
公开(公告)号：US20130215308A1
公开(公告)日：2013-08-22
申请号：US13749673
申请日：2013-01-24
申请人： Hitachi, Ltd.
发明人： Tomoyasu Furukawa , Tomohiro Saito , Yusuke Nonaka
IPC分类号： H04N5/374
CPC分类号： H01L27/14643 , H01L27/14603 , H01L27/14609 , H01L29/7816 , H04N5/3559 , H04N5/361 , H04N5/374 , H04N5/37452
摘要： A solid-state image sensing device is configured such that a first voltage is applied to a first conductivity type semiconductor region and a second voltage is applied to source-drain regions having a second conductivity type of the MOS capacitance to apply inverse bias between the semiconductor region and the source-drain regions of the MOS capacitance.

10. 发明授权

US08984235B2 Storage apparatus and control method for storage apparatus 有权
标题翻译：存储装置的存储装置和控制方法
公开(公告)号：US08984235B2
公开(公告)日：2015-03-17
申请号：US13701656
申请日：2012-11-14
申请人： Hitachi, Ltd.
发明人： Shintaro Kudo , Yusuke Nonaka , Masanori Takada
IPC分类号： G06F12/10 , G06F3/06 , G06F12/08
CPC分类号： G06F3/0626 , G06F3/0659 , G06F3/067 , G06F12/0813 , G06F12/0868 , G06F12/0871 , G06F2212/222 , G06F2212/282 , G06F2212/461 , G06F2212/463
摘要： An exemplary storage apparatus of the invention includes storage devices for storing data of block I/O commands and file I/O commands and a controller including a block cache area and a file cache area. The controller creates block I/O commands from file I/O commands and accesses the storage devices in accordance with the created block I/O commands. In a case where the file cache area is lacking an area to cache first data of a received first file I/O command, the controller chooses one of a first cache method that newly creates a free area in the file cache area to cache the first data in the file cache area and a second cache method that caches the first data in the block cache area without caching the first data in the file cache area.
摘要翻译：本发明的示例性存储装置包括用于存储块I / O命令和文件I / O命令的数据的存储装置和包括块高速缓存区域和文件高速缓存区域的控制器。控制器从文件I / O命令创建块I / O命令，并根据创建的块I / O命令访问存储设备。在文件缓存区域缺少高速缓存接收的第一文件I / O命令的第一数据的区域的情况下，控制器选择在文件高速缓存区域中新创建空闲区域的第一高速缓存方法之一，以缓存第一文件I / 文件高速缓存区域中的数据和缓存第一数据在块高速缓存区域中而不缓存文件高速缓存区域中的第一数据的第二高速缓存方法。

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