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1. 发明授权

US07978518B2 Hierarchical common source line structure in NAND flash memory 有权
标题翻译： NAND闪存中的分层公共源线结构
公开(公告)号：US07978518B2
公开(公告)日：2011-07-12
申请号：US12337038
申请日：2008-12-17
申请人： Hong-Beom Pyeon , Jin-Ki Kim
发明人： Hong-Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/30
摘要： Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.
摘要翻译：通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。对于源行页面编程，分发线可以称为全局公用源线（GCSL）。在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

2. 发明申请

US20110235424A1 HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY 有权
标题翻译： NAND FLASH存储器中的分层通用源结构
公开(公告)号：US20110235424A1
公开(公告)日：2011-09-29
申请号：US13154891
申请日：2011-06-07
申请人： Hong-Beom Pyeon , Jin-ki Kim
发明人： Hong-Beom Pyeon , Jin-ki Kim
IPC分类号： G11C16/10
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/30
摘要： Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.
摘要翻译：通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。对于源行页面编程，分发线可以称为全局公用源线（GCSL）。在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

3. 发明申请

US20090161437A1 HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY 有权
标题翻译： NAND FLASH存储器中的分层通用源结构
公开(公告)号：US20090161437A1
公开(公告)日：2009-06-25
申请号：US12337038
申请日：2008-12-17
申请人： Hong-Beom Pyeon , Jin-ki Kim
发明人： Hong-Beom Pyeon , Jin-ki Kim
IPC分类号： G11C16/04 , G11C5/14 , G11C16/06
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/30
摘要： Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.
摘要翻译：通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。对于源行页面编程，分发线可以称为全局公用源线（GCSL）。在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

4. 发明授权

US08675410B2 Hierarchical common source line structure in NAND flash memory 有权
标题翻译： NAND闪存中的分层公共源线结构
公开(公告)号：US08675410B2
公开(公告)日：2014-03-18
申请号：US13481888
申请日：2012-05-28
申请人： Hong-Beom Pyeon , Jin-Ki Kim
发明人： Hong-Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/30
摘要： Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.
摘要翻译：通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。对于源行页面编程，分发线可以称为全局公用源线（GCSL）。在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

5. 发明授权

US08208306B2 Hierarchical common source line structure in NAND flash memory 有权
标题翻译： NAND闪存中的分层公共源线结构
公开(公告)号：US08208306B2
公开(公告)日：2012-06-26
申请号：US13154891
申请日：2011-06-07
申请人： Hong-Beom Pyeon , Jin-ki Kim
发明人： Hong-Beom Pyeon , Jin-ki Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/30
摘要： Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.
摘要翻译：通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。对于源行页面编程，分发线可以称为全局公用源线（GCSL）。在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

6. 发明授权

US07894294B2 Operational mode control in serial-connected memory based on identifier 有权
标题翻译：基于标识符的串行存储器中的操作模式控制
公开(公告)号：US07894294B2
公开(公告)日：2011-02-22
申请号：US12352009
申请日：2009-01-12
申请人： Hong-Beom Pyeon
发明人： Hong-Beom Pyeon
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C5/04 , G11C7/10 , G11C7/1078 , G11C16/30
摘要： Applying an adapted block isolation method to serial-connected memory components may mitigate the effects of leakage current in serial-connected non-volatile memory devices. Responsive to determining that a given memory component is not an intended destination of a command, a plurality of core components of the given memory component may be placed in a low power consumption mode, while maintaining input/output components in an active operational mode. Conveniently, aspects of the disclosed system reduce off current without adding many logic blocks into the memory devices.
摘要翻译：将适配的块隔离方法应用于串行连接的存储器组件可以减轻串联连接的非易失性存储器件中的漏电流的影响。响应于确定给定存储器组件不是命令的预期目的地，给定存储器组件的多个核心组件可以被置于低功耗模式中，同时将输入/输出组件保持在主动操作模式。方便地，所公开的系统的方面减少了电流，而不会在存储器件中增加许多逻辑块。

7. 发明申请

US20070079147A1 Power up circuit with low power sleep mode operation 有权
标题翻译：通过低功耗睡眠模式操作启动电路
公开(公告)号：US20070079147A1
公开(公告)日：2007-04-05
申请号：US11238973
申请日：2005-09-30
申请人： Hong-Beom Pyeon , Peter Vlasenko
发明人： Hong-Beom Pyeon , Peter Vlasenko
IPC分类号： G06F1/00
CPC分类号： G06F1/24 , G06F1/3203 , H02J9/005
摘要： A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.
摘要翻译：一种在省电模式下降低功耗的上电电路，同时保持表示电源电压令人满意的有效标志信号。这是通过在省电模式期间关闭上电电路并且使用状态保持电路来响应于掉电信号来维持有效标志信号来实现的。状态保持电路响应于上电电路的内部节点，以在内部节点达到预定电平时产生有效标志信号。掉电信号可以是睡眠模式信号和深度掉电信号中的一个或两个。状态保持包括用于将有效标志信号保持在省电模式中的超控电路，以及用于在省电模式退出时至少快速复位上电电路的内部节点的恢复电路。

8. 发明授权

US08068382B2 Semiconductor memory with multiple wordline selection 有权
标题翻译：具有多种字线选择的半导体存储器
公开(公告)号：US08068382B2
公开(公告)日：2011-11-29
申请号：US12564492
申请日：2009-09-22
申请人： Hong-Beom Pyeon
发明人： Hong-Beom Pyeon
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/20
摘要： A semiconductor memory circuit, comprising: a memory array, the memory array including a plurality of wordlines each connected to a respective row of cells and a plurality of bitlines each connected to a respective column of cells. The semiconductor memory circuit also comprises at least one row decoder for selecting a group of wordlines within the plurality of wordlines; and a plurality of driver circuits for driving the plurality of bitlines respectively and setting the cells connected to the group of wordlines to a predetermined logic state. Also, a method for presetting at least part of a memory array, the memory array comprising a plurality of wordlines each connected to a respective row of cells. The method comprises selecting a group of wordlines within the plurality of wordlines; and simultaneously setting memory cells connected to the group of wordlines to a predetermined logic state.
摘要翻译：一种半导体存储器电路，包括：存储器阵列，所述存储器阵列包括各自连接到相应行单元的多个字线，以及多个位线，每个位线连接到相应的单元格列。所述半导体存储器电路还包括用于选择所述多个字线内的一组字线的至少一个行解码器; 以及多个驱动电路，用于分别驱动多个位线，并将连接到该组字线的单元设置为预定的逻辑状态。此外，一种用于预设存储器阵列的至少一部分的方法，所述存储器阵列包括多个字线，每个字线连接到相应行的单元。该方法包括选择多个字线内的一组字线; 并且将连接到该字线组的存储单元同时设置为预定的逻辑状态。

9. 发明申请

US20090185434A1 OPERATIONAL MODE CONTROL IN SERIAL-CONNECTED MEMORY BASED ON IDENTIFIER 有权
标题翻译：基于标识符的串行连接存储器中的操作模式控制
公开(公告)号：US20090185434A1
公开(公告)日：2009-07-23
申请号：US12352009
申请日：2009-01-12
申请人： Hong-Beom Pyeon
发明人： Hong-Beom Pyeon
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/1051 , G11C5/04 , G11C7/10 , G11C7/1078 , G11C16/30
摘要： Applying an adapted block isolation method to serial-connected memory components may mitigate the effects of leakage current in serial-connected non-volatile memory devices. Responsive to determining that a given memory component is not an intended destination of a command, a plurality of core components of the given memory component may be placed in a low power consumption mode, while maintaining input/output components in an active operational mode. Conveniently, aspects of the disclosed system reduce off current without adding many logic blocks into the memory devices.
摘要翻译：将适配的块隔离方法应用于串行连接的存储器组件可以减轻串联连接的非易失性存储器件中的漏电流的影响。响应于确定给定存储器组件不是命令的预期目的地，给定存储器组件的多个核心组件可以被置于低功耗模式中，同时将输入/输出组件保持在主动操作模式。方便地，所公开的系统的方面减少了电流，而不会在存储器件中增加许多逻辑块。

10. 发明申请

US20070030749A1 Voltage down converter for high speed memory 有权
公开(公告)号：US20070030749A1
公开(公告)日：2007-02-08
申请号：US11195641
申请日：2005-08-03
申请人： Hong-Beom Pyeon , Bruce Millar
发明人： Hong-Beom Pyeon , Bruce Millar
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/147 , G11C7/20 , G11C11/4072 , G11C11/4074
摘要： A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

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