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1. 发明授权

US08797073B2 Delay locked loop circuit and integrated circuit including the same 有权
标题翻译：延迟锁定环电路和集成电路包括相同
公开(公告)号：US08797073B2
公开(公告)日：2014-08-05
申请号：US12981256
申请日：2010-12-29
申请人： Min-Su Park , Hoon Choi
发明人： Min-Su Park , Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.
摘要翻译：延迟锁定环（DLL）电路包括定时脉冲发生单元，其被配置为响应于源时钟而在延迟移位更新周期期间产生顺序脉冲的多个定时脉冲，其中所产生的定时脉冲的数量根据到源时钟的频率; 时钟延迟单元，被配置为将源时钟的相位与由每个定时脉冲定义的时间点的反馈时钟的相位进行比较，并且延迟对应于所述定时脉冲的上升沿或下降沿的内部时钟的相位源时钟，根据比较结果; 以及延迟复制模型单元，被配置为反映所述时钟延迟单元的输出时钟上的内部时钟路径的实际延迟条件，并输出所述反馈时钟。

2. 发明授权

US08624643B2 Semiconductor memory apparatus 失效
标题翻译：半导体存储装置
公开(公告)号：US08624643B2
公开(公告)日：2014-01-07
申请号：US11824360
申请日：2007-06-29
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A semiconductor memory apparatus includes a phase comparator configured to compare phases of rising and falling feedback clocks with that of a reference clock, a delay circuit configured to delay the reference clock by a predetermined time based on a comparison result of the phase comparator to thereby generate rising and falling delayed clocks, a clock transmission block configured to invert the rising delayed clock outputted from the delay circuit when the rising and falling feedback clocks have substantially different phases, a duty compensator configured to compensate a duty ratio from outputs of the clock transmitting block to generate a delay locked clock having a compensated duty ratio, and a delay model configured to delay an output and an inverse output of the duty compensator by a modeled delay time respectively to generate the rising and falling feedback clocks.
摘要翻译：半导体存储装置包括相位比较器，被配置为将上升和下降反馈时钟的相位与参考时钟的相位进行比较;延迟电路，被配置为基于相位比较器的比较结果将参考时钟延迟预定时间，由此产生上升和下降延迟时钟，时钟传输块，配置为当上升和下降反馈时钟具有实质上不同的相位时，反相从延迟电路输出的上升延迟时钟;配置为补偿占空比与时钟发送块的输出以产生具有补偿占空比的延迟锁定时钟，以及延迟模型，被配置为分别延迟占空比补偿器的输出和反相输出模拟延迟时间以产生上升和下降反馈时钟。

3. 发明授权

US08562197B2 Backlight apparatus and display apparatus including the same 有权
公开(公告)号：US08562197B2
公开(公告)日：2013-10-22
申请号：US12960890
申请日：2010-12-06
申请人： Hoon Choi , Kwang-youn Kim
发明人： Hoon Choi , Kwang-youn Kim
IPC分类号： F21V8/00
CPC分类号： G02F1/133603 , G02B6/0083 , G02B6/009 , G09G3/3406 , H05K1/115 , H05K1/181 , H05K2201/0397 , H05K2201/10106 , H05K2201/10189 , Y02P70/611
摘要： A backlight apparatus includes a substrate which includes a plurality of layers. A plurality of light emitting modules are arranged on a top layer of the plurality of layers closest to a light guide panel, and a plurality of wires penetrates through the plurality of layers to electrically connect the light emitting modules and a plurality of driving units. Accordingly, the width of the substrate of an edge type backlight apparatus which can provide local dimming is reduced. Therefore, the display apparatus using the edge type backlight apparatus can be slim even if it is designed to provide local dimming.

4. 发明申请

US20130208547A1 APPARATUSES AND METHODS FOR LINE CHARGE SHARING 有权
标题翻译：线路充电共享的装置和方法
公开(公告)号：US20130208547A1
公开(公告)日：2013-08-15
申请号：US13369928
申请日：2012-02-09
申请人： Hoon Choi
发明人： Hoon Choi
IPC分类号： G11C7/10 , G11C7/12
CPC分类号： H03K19/0008 , G11C7/1048 , G11C7/12 , G11C8/08 , H03K19/0175
摘要： Apparatuses and methods for charge sharing between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing circuit, The charge sharing circuit may be coupled to the first line and the second line and configured to receive a first data signal and a second data signal. The charge sharing circuit may be further configured to cause charge to be shared between the first line and the second line responsive, at least in part, to the first data signal and the second data signal having different logic levels.
摘要翻译：公开了信号线之间电荷共享的装置和方法。示例性装置可以包括第一和第二线路以及电荷共享电路。电荷共享电路可以耦合到第一线路和第二线路并且被配置为接收第一数据信号和第二数据信号。电荷共享电路还可以被配置为至少部分地响应于具有不同逻辑电平的第一数据信号和第二数据信号，使电荷在第一线路和第二线路之间共享。

5. 发明授权

US08390351B2 Delay locked loop circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的延迟锁定环电路
公开(公告)号：US08390351B2
公开(公告)日：2013-03-05
申请号：US12971813
申请日：2010-12-17
申请人： Hoon Choi , Hyun Woo Lee
发明人： Hoon Choi , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： G11C7/222 , G11C7/1072
摘要： Various embodiments of a delay locked loop circuit of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the delay locked loop circuit may include an input correction unit configured to correct a duty ratio of an input clock based on a duty control signal and generate a reference clock; a delay line configured to delay the reference clock by a delay time and generate a delay locked clock; an output correction unit configured to correct a duty ratio of the delay locked clock based on the duty control signal and generate a corrected clock; and a control signal generation unit configured to generate the duty control signal when a correction activation signal is enabled.
摘要翻译：公开了半导体存储装置的延迟锁定环电路的各种实施例。在一个示例性实施例中，延迟锁定环电路可以包括：输入校正单元，被配置为基于占空比控制信号校正输入时钟的占空比并产生参考时钟; 延迟线，被配置为将所述参考时钟延迟延迟时间并产生延迟锁定时钟; 输出校正单元，被配置为基于所述占空比控制信号校正所述延迟锁定时钟的占空比，并生成校正时钟; 以及控制信号生成单元，被配置为当校正激活信号被使能时产生占空比控制信号。

6. 发明申请

US20120188444A1 CONVERSION AND PROCESSING OF DEEP COLOR VIDEO IN A SINGLE CLOCK DOMAIN 有权
标题翻译：深度色彩视频在单个时钟域的转换和处理
公开(公告)号：US20120188444A1
公开(公告)日：2012-07-26
申请号：US13217138
申请日：2011-08-24
申请人： Hoon Choi , Daekyeung Kim , Wooseung Yang , Young Il Kim
发明人： Hoon Choi , Daekyeung Kim , Wooseung Yang , Young Il Kim
IPC分类号： H04N7/01
CPC分类号： G09G5/006 , G09G3/2096 , G09G5/02 , G09G5/12 , G09G2340/04 , G09G2340/0428 , G09G2340/10 , G09G2360/02
摘要： Embodiments of the invention are generally directed to conversion and processing of deep color video in a single clock domain. An embodiment of a method includes receiving one or more video data streams, the one or more video data streams including a first video data stream, the first video data stream being clocked at a frequency of a link clock signal. The method further includes converting the first video data stream into a converted video data stream having a modified data format, wherein the modified data format includes transfer of a single pixel of data in one cycle of the link clock signal and the insertion of null data to fill empty cycles of the converted video data stream, and generation of a valid data signal to distinguish between valid video data and the null data in the converted video data stream. The method further includes processing the converted video data stream according to the frequency of the link clock signal to generate a processed data stream from the converted video data stream, wherein processing includes using the valid data signal to identify valid video data.
摘要翻译：本发明的实施例一般涉及在单个时钟域中的深色视频的转换和处理。一种方法的实施例包括接收一个或多个视频数据流，所述一个或多个视频数据流包括第一视频数据流，所述第一视频数据流以链路时钟信号的频率被计时。该方法还包括将第一视频数据流转换成具有修改的数据格式的转换的视频数据流，其中修改的数据格式包括在链路时钟信号的一个周期中传输单个像素的数据，并将空数据插入到填充经转换的视频数据流的空循环，以及生成有效数据信号以区分转换后的视频数据流中的有效视频数据和空数据。该方法还包括根据链路时钟信号的频率处理转换后的视频数据流，以从经转换的视频数据流生成经处理的数据流，其中处理包括使用有效数据信号来识别有效视频数据。

7. 发明申请

US20120182473A1 MECHANISM FOR CLOCK RECOVERY FOR STREAMING CONTENT BEING COMMUNICATED OVER A PACKETIZED COMMUNICATION NETWORK 审中-公开
标题翻译：用于通过封装通信网络传播的内容流的时钟恢复机制
公开(公告)号：US20120182473A1
公开(公告)日：2012-07-19
申请号：US13339339
申请日：2011-12-28
申请人： Gyudong Kim , Hoon Choi , Richard J. Wilcox , Chandlee Harrell
发明人： Gyudong Kim , Hoon Choi , Richard J. Wilcox , Chandlee Harrell
IPC分类号： H04N5/06 , H04L7/00
摘要： A mechanism for facilitating clock recovery for streaming content over a packetized network is described. A method of embodiments includes receiving an estimated data stream at a first device. The estimated data stream may include estimated data format information relating to a data stream expected to be received at the first device. The method may further include performing, at the first device, clock regeneration of the estimated data stream based on the estimated data format information. The clock regeneration may include performing clock recovery of the estimated data stream.
摘要翻译：描述了一种用于促进在分组化网络上流式传输内容的时钟恢复的机制。实施例的方法包括在第一设备处接收估计的数据流。估计数据流可以包括与预期在第一设备处接收的数据流有关的估计数据格式信息。该方法还可以包括在第一设备处，基于估计的数据格式信息执行估计数据流的时钟再生。时钟再生可以包括执行估计数据流的时钟恢复。

8. 发明授权

US08185739B2 Method and system for detecting successful authentication of multiple ports in a time-based roving architecture 有权
标题翻译：用于检测基于时间的流动结构中多个端口成功认证的方法和系统
公开(公告)号：US08185739B2
公开(公告)日：2012-05-22
申请号：US12351712
申请日：2009-01-09
申请人： Myoung Hwan Kim , Hoon Choi
发明人： Myoung Hwan Kim , Hoon Choi
IPC分类号： H04L9/32
CPC分类号： H04N7/163 , H04N21/4122 , H04N21/4367
摘要： In one embodiment of the present invention, a method includes authenticating an HDCP transmitting device at a first port of an HDCP receiving device. A port of the HDCP receiving device is connected to a pipe of an HDCP architecture of the HDCP receiving device at a first time. A synchronization signal is received from the HDCP transmitting device at the port of the HDCP receiving device at a second time. A loss of synchronization between the HDCP transmitting device and the HDCP receiving device is detected when the time-span between the first time and the second time is not greater than the period of time between synchronization signals sent from the HDCP transmitting device. A re-authentication is initiated between the HDCP transmitting device and the HDCP receiving device in response to detecting the loss of synchronization.
摘要翻译：在本发明的一个实施例中，一种方法包括在HDCP接收设备的第一端口处认证HDCP发送设备。 HDCP接收设备的端口在第一时间连接到HDCP接收设备的HDCP架构的管道。第二次在HDCP接收装置的端口从HDCP发送装置接收同步信号。当第一时间和第二时间之间的时间跨度不大于从HDCP发送装置发送的同步信号之间的时间段时，检测出HDCP发送装置与HDCP接收装置之间的同步丢失。响应于检测到同步丢失，在HDCP发送设备和HDCP接收设备之间启动重新认证。

9. 发明申请

US20120007639A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120007639A1
公开(公告)日：2012-01-12
申请号：US12881541
申请日：2010-09-14
申请人： Min-Su PARK , Hoon Choi
发明人： Min-Su PARK , Hoon Choi
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , G11C7/222
摘要： A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals.
摘要翻译：半导体器件包括：复位信号发生器，被配置为根据外部时钟的频率改变多个复位信号中的激活信号数;多个混合控制信号发生器，被配置为产生多个第一和第二混合控制信号以及时钟混频器，被配置为通过混合第一驱动时钟和第二驱动时钟来产生混频时钟，其中通过根据多个第一混频控制信号驱动外部时钟的正时钟来产生第一驱动时钟，以及通过根据多个第二混合控制信号驱动外部时钟的负时钟来产生第二驱动时钟。

10. 发明授权

US07984369B2 Concurrent code checker and hardware efficient high-speed I/O having built-in self-test and debug features 有权
标题翻译：兼容的代码检查器和硬件高效的高速I / O，具有内置的自检和调试功能
公开(公告)号：US07984369B2
公开(公告)日：2011-07-19
申请号：US11656331
申请日：2007-01-19
申请人： Chinsong Sul , Hoon Choi , Gijung Ahn
发明人： Chinsong Sul , Hoon Choi , Gijung Ahn
IPC分类号： G06F11/00 , H03M13/00 , H04L1/00
CPC分类号： H03M5/145 , H03M13/09 , H03M13/6325
摘要： Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.
摘要翻译：用于测试高速输入/输出系统中的错误的方法，设备和系统。系统和设备可以包括并发代码检查器，用于通过包括数据包的数据流的数据包静态属性和动态属性来检查编码数据分组中的错误。方法可以涉及使用数据包静态属性和包括数据包的数据流的动态属性检测无效编码包。使用不受保护条件优化并发代码检查器逻辑的设计的方法，以及具有降低逻辑元件和半导体面积要求的并行代码检查器电路的方法。

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