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    • 9. 发明申请
    • Semiconductor Memory Devices Having Strapping Contacts
    • 具有捆扎触头的半导体存储器件
    • US20130187119A1
    • 2013-07-25
    • US13630505
    • 2012-09-28
    • Jung-in KimJae-hee OhJun-hyok KongSung-ho EunYong-tae Oh
    • Jung-in KimJae-hee OhJun-hyok KongSung-ho EunYong-tae Oh
    • H01L45/00
    • H01L45/06G11C5/06G11C8/10G11C11/16G11C13/0004H01L27/101H01L2924/0002H01L2924/00
    • Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions. The active patterns contact the first interconnection lines through strapping contacts in the strapping regions.
    • 提供了具有捆扎触点的半导体存储器件,器件包括在第一方向上的相邻单元区域之间的单元区域和绑带区域。 在整个单元区域和捆扎区域中沿着第一方向延伸的活动图案在与第一方向相交的第二方向上彼此间隔开。 在整个单元区域和捆扎区域沿第一方向延伸的第一互连线在第二方向上彼此间隔开,同时与有源图案重叠。 沿第二方向延伸的第二互连线与单元区域中的有源图案和第一互连线相交。 第二互连线在第一方向上彼此间隔开。 存储单元位于单元区域中的第一和第二互连线的交叉部分处。 有源图案通过捆扎区域中的捆扎触头接触第一互连线。
    • 10. 发明授权
    • Memory devices including decoders having different transistor channel dimensions and related devices
    • 存储器件包括具有不同晶体管沟道尺寸的解码器和相关器件
    • US08493769B2
    • 2013-07-23
    • US12724465
    • 2010-03-16
    • Sung-ho EunJae-Hee Oh
    • Sung-ho EunJae-Hee Oh
    • G11C11/00
    • G11C13/003G11C8/10G11C11/1659G11C13/0004G11C2213/72G11C2213/76
    • An integrated circuit memory device includes a memory cell array comprising memory cells having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines. Each of the conductive lines electrically couple a respective one of the pass transistors to ones of the memory cells. Each of the memory cells has a line resistance defined by a portion of the corresponding one of the conductive lines extending between the memory cell and the pass transistor coupled thereto. Ones of the memory cells having greater line resistances are coupled to ones of the pass transistors having greater channel widths and/or shorter channel lengths than ones of the memory cells having smaller line resistances. Each of the memory cells may also include a diode therein, and ones of the memory cells having greater line resistances may include diodes having lower resistances. Related devices are also discussed.
    • 集成电路存储器件包括存储单元阵列,其包括其中具有各自数据存储区域的存储单元,具有不同沟道宽度和/或沟道长度的多个传输晶体管,以及多条导线。 每个导线将相应的一个通过晶体管电耦合到一个存储单元。 每个存储单元具有由在存储单元和与其耦合的通过晶体管之间延伸的相应一条导线的一部分限定的线电阻。 具有较大线路电阻的存储单元的一部分与具有较小线路电阻的存储单元的通道宽度和/或较短沟道长度的通路晶体管中的一个耦合。 每个存储单元还可以包括二极管,并且具有较大线路电阻的存储单元中的一个可以包括具有较低电阻的二极管。 还讨论了相关设备。