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1. 发明授权

US10643945B2 Pitch translation architecture for semiconductor package including embedded interconnect bridge 有权
公开(公告)号：US10643945B2
公开(公告)日：2020-05-05
申请号：US15857515
申请日：2017-12-28
申请人： Intel Corporation
发明人： Andrew Collins , Bharat P. Penmecha , Rajasekaran Swaminathan , Ram Viswanath
IPC分类号： H01L23/538 , H01L23/528 , H01L23/498 , H01L23/00 , H01L25/065 , H01L25/18
CPC分类号： H01L23/5283 , H01L23/49838 , H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L23/5385 , H01L24/17 , H01L24/23 , H01L25/0655 , H01L25/18
摘要： Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

2. 发明授权

US09832876B2 CPU package substrates with removable memory mechanical interfaces 有权
公开(公告)号：US09832876B2
公开(公告)日：2017-11-28
申请号：US14575775
申请日：2014-12-18
申请人： INTEL CORPORATION
发明人： Mani Prakash , Thomas T. Holden , Jeffory L. Smalley , Ram S. Viswanath , Bassam N. Coury , Dimitrios Ziakas , Chong J. Zhao , Jonathan W. Thibado , Gregorio R. Murtagian , Kuang C. Liu , Rajasekaran Swaminathan , Zhichao Zhang , John M. Lynch , David J. Llapitan , Sanka Ganesan , Xiang Li , George Vergis
IPC分类号： H05K1/18 , H01L23/00 , H01R12/71 , H01R12/79
CPC分类号： H05K1/181 , H01L23/00 , H01L23/498 , H01L2224/16225 , H01L2924/15311 , H01R12/712 , H01R12/79 , H05K2201/10159 , H05K2201/10325 , Y02P70/611
摘要： Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

3. 发明授权

US09603247B2 Electronic package with narrow-factor via including finish layer 有权
公开(公告)号：US09603247B2
公开(公告)日：2017-03-21
申请号：US14456606
申请日：2014-08-11
申请人： Intel Corporation
发明人： Rajasekaran Swaminathan , Sairam Agraharam , Amruthavalli Pallavi Alur , Ram Viswanath , Wei-Lun Kane Jen
IPC分类号： H05K1/09 , H05K1/11 , H05K3/24 , H01L23/00 , H05K3/40
CPC分类号： H05K1/112 , H01L23/5381 , H01L23/5385 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/29 , H01L24/32 , H01L24/81 , H01L2224/0401 , H01L2224/05647 , H01L2224/1132 , H01L2224/131 , H01L2224/13294 , H01L2224/133 , H01L2224/1403 , H01L2224/16165 , H01L2224/16235 , H01L2224/16237 , H01L2224/16501 , H01L2224/29082 , H01L2224/32225 , H01L2224/73104 , H01L2224/81191 , H01L2224/81193 , H01L2224/81444 , H01L2224/81464 , H01L2224/83101 , H01L2224/83191 , H05K1/09 , H05K1/113 , H05K1/185 , H05K3/243 , H05K3/244 , H05K3/4046 , H05K2201/09472 , H05K2201/10189 , H01L2924/00014 , H01L2924/014 , H01L2924/01079
摘要： This disclosure relates generally to an electronic package and methods that include an electrically conductive pad, a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, and a via. The via may be formed within the package insulator layer and electrically coupled to the electrically conductive pad. The via may include a conductor extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end and a finish layer secured to the second end of the conductor, the finish layer including a gold compound.

4. 发明申请

US20160079150A1 TECHNIQUES AND CONFIGURATIONS ASSOCIATED WITH A PACKAGE LOAD ASSEMBLY 有权
标题翻译：与包装装配相关的技术和配置
公开(公告)号：US20160079150A1
公开(公告)日：2016-03-17
申请号：US14484896
申请日：2014-09-12
申请人： Intel Corporation
发明人： Gaurav Chawla , Joshua D. Heppner , Vijaykumar Krithivasan , Michael Garcia , Kuang C. Liu , Rajasekaran Swaminathan
IPC分类号： H01L23/498 , H01L23/36 , H01L21/48 , B23P15/26
CPC分类号： H05K7/20 , H01L23/3675 , H01L23/4006 , H01L23/433 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H01L2924/16152 , H01L2924/00
摘要： Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.
摘要翻译：本公开的实施例涉及与封装负载组件相关联的技术和配置。在一个实施例中，包装负载组件可以包括框架，该框架被配置为围绕包装衬底的管芯区域形成周边，该封装衬底具有构造成与封装衬底的表面耦合的第一表面和与第一表面相对设置的第二表面。框架可以包括设置在第二表面上的可变形构件，其可以被配置为与散热器的底座相耦合，以经由框架分布施加在散热器和封装衬底之间的力，并且可以在应用力，其可以允许散热器的底部接触在封装衬底的管芯区域内的集成散热器的表面。

5. 发明授权

US09118151B2 Interconnect cable with edge finger connector 有权
标题翻译：互连电缆与边缘指接头
公开(公告)号：US09118151B2
公开(公告)日：2015-08-25
申请号：US13870938
申请日：2013-04-25
申请人： Intel Corporation
发明人： Donald T. Tran , Rajasekaran Swaminathan
IPC分类号： H01R12/00 , H01R12/71 , H01R12/81 , H01R13/6592
CPC分类号： H01R12/721 , H01R12/714 , H01R12/81 , H01R13/6581 , H01R13/6592 , H01R43/205 , Y10T29/49174 , Y10T29/49176
摘要： Embodiments of the present disclosure are directed to an interconnect cable including a edge finger connector, and associated configurations and methods. The edge finger connector may be disposed at a first end of the interconnect cable and may connect the interconnect cable to an edge finger included in or coupled to a package substrate. The package substrate may be included in a processor package assembly, and a processor may be mounted on the substrate. The interconnect cable may include one or more elongate conductors, with contacts directly coupled to respective conductors. A second connector may be disposed at a second end of the interconnect cable, and may couple the interconnect cable to a small form-factor pluggable (SFP) case that is configured to connect the interconnect cable to an SFP cable. Other embodiments may be described and claimed.
摘要翻译：本公开的实施例涉及包括边缘指状连接器以及相关联的配置和方法的互连电缆。边缘指状连接器可以设置在互连电缆的第一端处，并且可以将互连电缆连接到包括在封装衬底中或耦合到封装衬底的边缘指状物。封装衬底可以包括在处理器封装组件中，并且处理器可以安装在衬底上。互连电缆可以包括一个或多个细长导体，其中触点直接耦合到相应的导体。第二连接器可以设置在互连电缆的第二端处，并且可以将互连电缆耦合到被配置为将互连电缆连接到SFP电缆的小型可插拔（SFP）壳体。可以描述和要求保护其他实施例。

6. 发明授权

US09010618B2 Magnetic attachment structure 有权
标题翻译：磁性附件结构
公开(公告)号：US09010618B2
公开(公告)日：2015-04-21
申请号：US13855100
申请日：2013-04-02
申请人： Intel Corporation
发明人： Aleksandar Aleksov , Rajasekaran Swaminathan , Ting Zhong
IPC分类号： B23K31/02 , H01L21/44 , H01F1/01 , B23K1/00 , B23K1/20 , H01L23/00
CPC分类号： H01F1/01 , B23K1/0016 , B23K1/20 , H01L24/05 , H01L24/13 , H01L24/75 , H01L24/81 , H01L2224/0401 , H01L2224/05547 , H01L2224/0556 , H01L2224/05599 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13584 , H01L2224/16225 , H01L2224/75264 , H01L2224/81192 , H01L2224/81222 , H01L2224/81234 , H01L2224/81815 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , Y10T428/24612 , H01L2924/00 , H01L2224/05552
摘要： The present disclosure relates to the field of fabricating microelectronic packages, wherein components of the microelectronic packages may have magnetic attachment structures comprising a magnetic component and a metal component. The magnetic attachment structure may be exposed to a magnetic field, which, through the vibration of the magnetic component, can heat the magnetic attachment structure, and which when placed in contact with a solder material can reflow the solder material and attach microelectronic components of the microelectronic package.
摘要翻译：本公开涉及制造微电子封装的领域，其中微电子封装的部件可具有包括磁性部件和金属部件的磁性附接结构。磁性附着结构可能暴露于磁场，通过磁性部件的振动可以加热磁性附着结构，并且当与焊料材料接触时，磁性附着结构可以回流焊料材料并附着微电子部件微电子封装。

7. 发明申请

US20210066240A1 CHIP WITH MAGNETIC INTERCONNECT ALIGNMENT 有权
公开(公告)号：US20210066240A1
公开(公告)日：2021-03-04
申请号：US16644762
申请日：2017-09-29
申请人： Intel Corporation
发明人： Rajasekaran Swaminathan
IPC分类号： H01L23/00 , H01L23/498
摘要： An electronic assembly, and a method for making the electronic assembly, includes a first electronic component, a second electronic component, and a plurality of interconnects. The plurality of interconnects electrically couple the first electronic component to the second electronic component. Each of the plurality of interconnects comprise one of a plurality of first magnetic components in physical alignment with an associated one of a plurality of second magnetic components, the plurality of second magnetic components being components of one of the second electronic component and the plurality of interconnects.

8. 发明申请

US20180270957A1 PRINTED CIRCUIT BOARD WITH A RECESS TO ACCOMMODATE DISCRETE COMPONENTS IN A PACKAGE 审中-公开
公开(公告)号：US20180270957A1
公开(公告)日：2018-09-20
申请号：US15459787
申请日：2017-03-15
申请人： Intel Corporation
发明人： Rajasekaran Swaminathan , Ram S. Viswanath
IPC分类号： H05K1/18 , H05K1/11 , H05K3/00 , H05K3/30 , H05K3/46
CPC分类号： H05K1/183 , H05K1/0216 , H05K1/113 , H05K1/141 , H05K3/0014 , H05K3/303 , H05K3/46 , H05K3/4697 , H05K2201/09036 , H05K2201/09072 , H05K2201/10628 , H05K2201/10719 , H05K2201/10734
摘要： Embodiments of the present disclosure provide techniques for a printed circuit board (PCB) with a recess to accommodate discrete components of a package attachable to the PCB, in accordance with some embodiments. In one embodiment, a PCB may include a recess disposed in at least a portion of the PCB, to receive at least a portion of a package. The package may be attachable to the PCB via a plurality of connectors. The connectors may be disposed on a side of the package that faces the PCB. The portion of the package may include one or more discrete components disposed on the side of the package that faces the PCB. The recess may have a depth to accommodate those discrete components that have a height that is greater than a height of the connectors. Other embodiments may be described and/or claimed.

9. 发明授权

US09615483B2 Techniques and configurations associated with a package load assembly 有权
公开(公告)号：US09615483B2
公开(公告)日：2017-04-04
申请号：US14484896
申请日：2014-09-12
申请人： Intel Corporation
发明人： Gaurav Chawla , Joshua D. Heppner , Vijaykumar Krithivasan , Michael Garcia , Kuang C. Liu , Rajasekaran Swaminathan
IPC分类号： H05K7/20 , H01L23/367 , H01L23/40 , H01L23/433
CPC分类号： H05K7/20 , H01L23/3675 , H01L23/4006 , H01L23/433 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H01L2924/16152 , H01L2924/00
摘要： Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.

10. 发明授权

US09478881B2 Snap connector for socket assembly and associated techniques and configurations 有权
标题翻译：用于插座组件和相关技术和配置的卡口连接器
公开(公告)号：US09478881B2
公开(公告)日：2016-10-25
申请号：US14642078
申请日：2015-03-09
申请人： Intel Corporation
发明人： Zhichao Zhang , Gaurav Chawla , Rajasekaran Swaminathan , Kemal Aygun , Li Sun
IPC分类号： H01R13/193 , H01R12/51 , H01R12/70 , H01R43/20
CPC分类号： H01R12/7076 , H01R43/205 , H05K7/1038
摘要： Embodiments of the present disclosure are directed towards a snap connector for socket assembly and associated techniques and configurations. In one embodiment, a socket assembly includes a socket body having a plurality of openings extending from a first side of the socket body to a second side of the socket body to provide an electrical pathway between the first side and the second side, the second side disposed opposite to the first side, wherein a holding portion of an individual opening of the plurality of openings adjacent to the first side of the socket body is shaped to hold a corresponding electrical contact of a die package by elastic force applied by the socket body to the electrical contact when the electrical contact is positioned within the holding portion. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及用于插座组件和相关技术和配置的卡扣连接器。在一个实施例中，插座组件包括插座主体，该插座主体具有从插座本体的第一侧延伸到插座主体的第二侧的多个开口，以在第一侧和第二侧之间提供电路径，第二侧与所述第一侧相对设置，其中所述多个开口的与所述插座主体的第一侧相邻的开口的保持部分成形为通过由所述插座主体施加的弹力来保持模具组件的对应电接触，当电触点位于保持部分内时的电接触。可以描述和/或要求保护其他实施例。

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