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    • 2. 发明申请
    • TECHNIQUES FOR SEGMENTING OF HARDWARE TRACE AND VERIFICATION OF INDIVIDUAL TRACE SEGMENTS
    • 硬件跟踪分类技术和个别追踪部分验证技术
    • US20140143745A1
    • 2014-05-22
    • US13680253
    • 2012-11-19
    • INTERNATIONAL BUSINESS MACHINES CORPORATION
    • Eitan MarcusChristopher SpandikowAvi Ziv
    • G06F17/50
    • G06F17/5022G06F2217/68
    • A logic verification program, method and system that segments simulation results and then processes the resulting segments separately, and optionally in parallel, reduces memory and other system requirements and improves efficiency of verification of digital logic designs. The verification process fixes up event dependency check for past-directed checkers by including additional information with each segment after an initial segment that describes at least a portion of a state of the logic design, so that resultant events in the current segment that are caused by events in the previous segment(s) can be traced back to those events. Future directed checks are fixed-up by either repeating a failed check with a concatenation of the current segment and a next segment, or by providing an overlap between segments to ensure that the expected time duration between a causative event and the resulting event are included within the same segment file.
    • 一个逻辑验证程序,方法和系统,分段模拟结果,然后单独处理结果段,并且可选地并行处理,减少了内存和其他系统需求,并提高了数字逻辑设计的验证效率。 验证过程通过在描述逻辑设计的状态的至少一部分的初始段之后包括每个段的附加信息来修复对过去定向检查器的事件依赖性检查,使得由当前段引起的结果事件由 前一个细分中的事件可以追溯到这些事件。 未来有针对性的检查是通过重复一个失败的检查与当前段和下一个段的连接,或通过在段之间提供重叠来确保事件事件和结果事件之间的预期持续时间被包括在 相同的段文件。