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1. 发明申请

US20190155771A1 TECHNIQUES FOR ISSUING INTERRUPTS IN A DATA PROCESSING SYSTEM WITH MULTIPLE SCOPES 审中-公开
公开(公告)号：US20190155771A1
公开(公告)日：2019-05-23
申请号：US16254239
申请日：2019-01-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Florian A. Auernhammer , Wayne M. Barrett , Robert A. Drehmel , Michael S. Siegel
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F2213/2412 , G06F2213/2414
摘要： A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.

2. 发明授权

US10248593B2 Techniques for handling interrupts in a processing unit using interrupt request queues 有权
公开(公告)号：US10248593B2
公开(公告)日：2019-04-02
申请号：US15613239
申请日：2017-06-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Florian A. Auernhammer , Daniel Wind
IPC分类号： G06F13/24 , G06F12/122
摘要： A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

3. 发明授权

US10114773B2 Techniques for handling interrupts in a processing unit using virtual processor thread groups and software stack levels 有权
公开(公告)号：US10114773B2
公开(公告)日：2018-10-30
申请号：US15816597
申请日：2017-11-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Richard L. Arndt , Florian A. Auernhammer
IPC分类号： G06F13/24 , G06F13/26 , G06F9/54 , G06F13/28 , G06F13/40 , G06F12/122
摘要： A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies a level, an event target number, and a number of bits to ignore. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

4. 发明授权

US09870329B2 Techniques for escalating interrupts in a data processing system 有权
公开(公告)号：US09870329B2
公开(公告)日：2018-01-16
申请号：US15339382
申请日：2016-10-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Richard L. Arndt , Florian A. Auernhammer
IPC分类号： G06F13/26 , G06F12/122 , G06F13/40 , G06F13/24 , G06F13/28 , G06F9/54
CPC分类号： G06F13/26 , G06F9/542 , G06F12/12 , G06F12/122 , G06F13/24 , G06F13/28 , G06F13/4068 , G06F2212/70
摘要： A method of handling interrupts includes receiving an event notification message (ENM) that specifies a level, an event target number (ETN), and a number of bits to ignore. A group of virtual processor threads that may be potentially interrupted are determined based on the ETN, the number of bits to ignore, and a process identifier when the level specified in the ENM corresponds to a user level. The ETN identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore when determining a group of virtual processor threads that may be potentially interrupted. In response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, an escalate message that includes an escalate event number is transmitted. The escalate event number is used to generate a subsequent ENM.

5. 发明授权

US09852091B2 Techniques for handling interrupts in a processing unit using virtual processor thread groups and software stack levels 有权
公开(公告)号：US09852091B2
公开(公告)日：2017-12-26
申请号：US15334857
申请日：2016-10-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Richard L. Arndt , Florian A. Auernhammer
IPC分类号： G06F13/24 , G06F13/26 , G06F12/122 , G06F13/40 , G06F13/28 , G06F9/54
CPC分类号： G06F13/26 , G06F9/542 , G06F12/12 , G06F12/122 , G06F13/24 , G06F13/28 , G06F13/4068 , G06F2212/70
摘要： A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies a level, an event target number, and a number of bits to ignore. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

6. 发明授权

US09817774B2 Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system 有权
公开(公告)号：US09817774B2
公开(公告)日：2017-11-14
申请号：US14744379
申请日：2015-06-19
申请人： International Business Machines Corporation
发明人： Florian A. Auernhammer , Joseph G. McDonald
IPC分类号： G06F13/16 , G06F13/362 , G06F13/40 , G06F13/376 , G06F13/42
CPC分类号： G06F13/1642 , G06F13/1673 , G06F13/362 , G06F13/376 , G06F13/4031 , G06F13/4068 , G06F13/4221
摘要： A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes N machines configured to handle requests from the requesting interconnect and for handling allocated responses from the serving interconnect, wherein each of the N machines has an allocated local count; a tracking entity configured to track priorities of the N machines for issuing received requests to the serving interconnect and for issuing received responses to the requesting interconnect based on the N local counts; a first arbiter configured to arbitrate the received requests to be issued to the serving interconnect based on the tracked priorities; and a second arbiter configured to arbitrate the received responses to be issued to the requesting interconnect based on the tracked priorities.

7. 发明授权

US08996840B2 I/O controller and method for operating an I/O controller 有权
标题翻译： I / O控制器和操作I / O控制器的方法
公开(公告)号：US08996840B2
公开(公告)日：2015-03-31
申请号：US13705404
申请日：2012-12-05
申请人： International Business Machines Corporation
发明人： Florian A. Auernhammer , Patricia M. Sagmeister
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/1063 , G06F12/0862 , G06F12/10 , G06F12/1027 , G06F12/1081 , G06F12/122 , G06F2212/50 , G06F2212/602
摘要： An I/O controller, coupled to a processing unit and to a memory, includes an I/O link interface configured to receive data packets having virtual addresses; an address translation unit having an address translator to translate received virtual addresses into real addresses by translation control entries and a cache allocated to the address translator to cache a number of the translation control entries; an I/O packet processing unit for checking the data packets received at the I/O link interface and for forwarding the checked data packets to the address translation unit; and a prefetcher to forward address translation prefetch information from a data packet received to the address translation unit; the address translator configured to fetch the translation control entry for the data packet by the address translation prefetch information from the allocated cache or, if the translation control entry is not available in the allocated cache, from the memory.
摘要翻译：耦合到处理单元和存储器的I / O控制器包括被配置为接收具有虚拟地址的数据分组的I / O链路接口; 地址转换单元，具有地址转换器，用于通过转换控制条目将接收到的虚拟地址转换成实际地址，以及分配给地址转换器的高速缓存来缓存多个转换控制条目; I / O分组处理单元，用于检查在I / O链路接口处接收的数据分组，并将检查的数据分组转发到地址转换单元; 以及预取器，用于将地址转换预取信息从接收到的数据分组转发到地址转换单元; 地址转换器被配置为通过来自分配的高速缓存的地址转换预取信息来获取数据分组的转换控制条目，或者如果转换控制条目在分配的高速缓存中不可用，则从存储器获取。

8. 发明授权

US10229075B2 Techniques for escalating interrupts in a processing unit using virtual processor thread groups and software stack levels 有权
公开(公告)号：US10229075B2
公开(公告)日：2019-03-12
申请号：US15824545
申请日：2017-11-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Richard L. Arndt , Florian A. Auernhammer
IPC分类号： G06F13/26 , G06F12/122 , G06F13/40 , G06F13/24 , G06F13/28 , G06F9/54 , G06F12/12
摘要： A method of handling interrupts includes receiving an event notification message (ENM) that specifies a level, an event target number (ETN), and a number of bits to ignore. A group of virtual processor threads that may be potentially interrupted are determined based on the ETN, the number of bits to ignore, and a process identifier when the level specified in the ENM corresponds to a user level. The ETN identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore when determining a group of virtual processor threads that may be potentially interrupted. In response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, an escalate message that includes an escalate event number is transmitted. The escalate event number is used to generate a subsequent ENM.

9. 发明授权

US10061723B2 Techniques for handling queued interrupts in a data processing system based on a saturation value 有权
公开(公告)号：US10061723B2
公开(公告)日：2018-08-28
申请号：US15340076
申请日：2016-11-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Richard L. Arndt , Florian A. Auernhammer
IPC分类号： G06F13/24 , G06F13/26 , G06F12/122 , G06F13/40 , G06F13/28 , G06F9/54
CPC分类号： G06F13/26 , G06F9/4881 , G06F9/542 , G06F12/12 , G06F12/122 , G06F13/24 , G06F13/28 , G06F13/4068 , G06F2212/70
摘要： A technique for handling queued interrupts includes accumulating, by an interrupt routing controller (IRC), respective backlog counts for respective event paths. The background counts track a number of events received but not delivered as interrupts to associated virtual processor (VP) threads upon which respective target interrupt handlers execute. An increment backlog (IB) message is received by the IRC. In response to receiving the IB message, the IRC determines an associated saturate value for an event path specified in the IB message. The IRC increments an associated backlog count for the event path specified in the IB message as long as the associated backlog count does not exceed the associated saturate value.

10. 发明授权

US09727498B2 Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system 有权
公开(公告)号：US09727498B2
公开(公告)日：2017-08-08
申请号：US14600556
申请日：2015-01-20
申请人： International Business Machines Corporation
发明人： Florian A. Auernhammer , Joseph G. McDonald
IPC分类号： G06F13/16 , G06F13/40
CPC分类号： G06F13/1642 , G06F13/1673 , G06F13/4027 , G06F13/4068
摘要： A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes a first interface configured to receive a read request and a number of dependent write requests that the read request depends on from the requesting interconnect; and an issuer configured to issue the received number of dependent write requests to the serving interconnect and for issuing the received read request to the serving interconnect after issuing the number of dependent write requests and before receiving write acknowledgments for the issued dependent write requests from the serving interconnect.

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