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1. 发明授权

US11152495B2 Integrated circuit heat dissipation using nanostructures 有权
公开(公告)号：US11152495B2
公开(公告)日：2021-10-19
申请号：US16587290
申请日：2019-09-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Alan B. Botula , Max L. Lifson , James A. Slinkman , Theodore G. Van Kessel , Randy L. Wolf
IPC分类号： H01L29/732 , H01L23/373 , H01L29/78 , H01L29/45 , H01L23/525 , H01L21/02 , H01L21/285 , H01L29/10 , H01L29/08 , H01L49/02 , H01L29/06 , H01L21/762 , B82Y10/00 , H01L29/417 , H01L29/41 , H01L23/367 , H01L21/48 , H01L21/288 , H01L21/3205 , H01L23/48 , H01L23/485 , H01L29/66
摘要： An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

2. 发明授权

US09646993B2 Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming 有权
公开(公告)号：US09646993B2
公开(公告)日：2017-05-09
申请号：US14834696
申请日：2015-08-25
申请人： International Business Machines Corporation
发明人： Peng Cheng , James S. Dunn , Blaine J. Gross , Qizhi Liu , James A. Slinkman
IPC分类号： H01L21/70 , H01L27/12 , H01L29/66 , H01L29/78 , H01L27/02 , H01L29/06 , H01L29/165 , H01L29/45 , H01L21/308 , H01L27/088
CPC分类号： H01L27/1203 , H01L21/3081 , H01L21/764 , H01L27/0207 , H01L27/088 , H01L27/1207 , H01L29/0649 , H01L29/165 , H01L29/456 , H01L29/66477 , H01L29/78 , H01L29/7842
摘要： Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set of trenches; a first oxide abutting the silicon substrate; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions; a gate structure overlying the second oxide between adjacent salicide regions; and a first contact contacting the gate structure; a second contact contacting one of the salicide regions; a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and an air gap in each of the set of trenches, the air gap surrounded by the third oxide.

3. 发明申请

US20150072504A1 HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS 有权
标题翻译：用于低失真电路应用的高线性SOI波形
公开(公告)号：US20150072504A1
公开(公告)日：2015-03-12
申请号：US14546058
申请日：2014-11-18
申请人： International Business Machines Corporation
发明人： Alan B. Botula , Jeffrey E. Hanrahan , Mark D. Jaffe , Alvin J. Joseph , Dale W. Martin , Gerd Pfeiffer , James A. Slinkman
IPC分类号： H01L21/762 , H01L21/324 , H01L21/265
CPC分类号： H01L21/76251 , H01L21/04 , H01L21/265 , H01L21/26506 , H01L21/324
摘要： According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
摘要翻译：根据本文的方法，在第一材料被植入之后，衬底的第一侧被注入第一材料，以将衬底的第一侧的结晶结构从第一结晶状态改变到第二结晶状态。在植入第一种材料之后，第二种材料沉积在基底的第一面上。绝缘体层的第一面在衬底的第一侧上与第二材料接合。在绝缘体层与第二材料结合之后，在绝缘体层的与绝缘体层的第一侧相对的第二侧上形成集成电路器件。集成电路器件进行热退火。第一种材料在退火过程中保持衬底的第一面的第二结晶状态。

4. 发明申请

US20150024570A1 SCALING OF BIPOLAR TRANSISTORS 有权
标题翻译：双极晶体管的放大
公开(公告)号：US20150024570A1
公开(公告)日：2015-01-22
申请号：US14508011
申请日：2014-10-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Alvin J. Joseph , Ramana M. Malladi , James A. Slinkman
IPC分类号： H01L29/66 , H01L21/311 , H01L21/02 , H01L21/762
CPC分类号： H01L29/66272 , G06F17/5009 , G06F17/5036 , G06F17/5068 , G06F2217/12 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/8249 , H01L27/0207 , H01L29/7322 , Y02P90/265
摘要： Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor.
摘要翻译：双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。设计双极晶体管的方法包括：选择双极晶体管的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管的缩放设计; 基于缩放之后双极晶体管的发射极的尺寸来确定双极晶体管的缩放设计的应力补偿是否需要; 并且如果需要对双极型晶体管的缩放设计的应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计的发射器布局级别的布局的布局，以产生压缩补偿的缩放设计双极晶体管。

5. 发明授权

US10109553B2 Integrated circuit heat dissipation using nanostructures 有权
公开(公告)号：US10109553B2
公开(公告)日：2018-10-23
申请号：US15471090
申请日：2017-03-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Alan B. Botula , Max L. Lifson , James A. Slinkman , Theodore G. Van Kessel , Randy L. Wolf
IPC分类号： H01L29/08 , H01L23/367 , H01L29/06 , H01L29/732 , H01L29/41 , H01L29/45
摘要： An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

6. 发明授权

US10068827B2 Integrated circuit heat dissipation using nanostructures 有权
公开(公告)号：US10068827B2
公开(公告)日：2018-09-04
申请号：US15401660
申请日：2017-01-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Alan B. Botula , Max L. Lifson , James A. Slinkman , Theodore G. Van Kessel , Randy L. Wolf
IPC分类号： H01L29/08 , H01L23/367 , H01L23/373 , H01L21/48 , H01L21/288 , H01L21/3205 , H01L21/02 , H01L29/41
摘要： An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

7. 发明授权

US09666701B2 Integrated circuit heat dissipation using nanostructures 有权
公开(公告)号：US09666701B2
公开(公告)日：2017-05-30
申请号：US15074165
申请日：2016-03-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Alan B. Botula , Max L. Lifson , James A. Slinkman , Theodore G. Van Kessel , Randy L. Wolf
IPC分类号： H01L29/08 , H01L29/732 , H01L23/367 , H01L23/373 , H01L29/78 , H01L29/45 , H01L23/525 , H01L21/02 , H01L21/285 , H01L21/762 , H01L49/02 , H01L29/06 , H01L29/10 , B82Y10/00 , H01L29/417 , H01L29/41 , H01L21/48 , H01L23/48 , H01L23/485
CPC分类号： H01L23/3677 , B82Y10/00 , H01L21/02112 , H01L21/02178 , H01L21/02189 , H01L21/02271 , H01L21/02488 , H01L21/02554 , H01L21/02603 , H01L21/02628 , H01L21/28518 , H01L21/2855 , H01L21/28568 , H01L21/2885 , H01L21/32051 , H01L21/32053 , H01L21/4882 , H01L21/7624 , H01L23/3731 , H01L23/3738 , H01L23/481 , H01L23/485 , H01L23/5256 , H01L28/20 , H01L29/0649 , H01L29/0676 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/413 , H01L29/41725 , H01L29/45 , H01L29/456 , H01L29/732 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

8. 发明授权

US09165819B2 High linearity SOI wafer for low-distortion circuit applications 有权
标题翻译：用于低失真电路应用的高线性SOI晶片
公开(公告)号：US09165819B2
公开(公告)日：2015-10-20
申请号：US14546058
申请日：2014-11-18
申请人： International Business Machines Corporation
发明人： Alan B. Botula , Jeffrey E. Hanrahan , Mark D. Jaffe , Alvin J. Joseph , Dale W. Martin , Gerd Pfeiffer , James A. Slinkman
IPC分类号： H01L21/76 , H01L21/04 , H01L21/762 , H01L21/265 , H01L21/324
CPC分类号： H01L21/76251 , H01L21/04 , H01L21/265 , H01L21/26506 , H01L21/324
摘要： According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
摘要翻译：根据本文的方法，在第一材料被植入之后，衬底的第一侧被注入第一材料，以将衬底的第一侧的结晶结构从第一结晶状态改变到第二结晶状态。在植入第一种材料之后，第二种材料沉积在基底的第一面上。绝缘体层的第一面在衬底的第一侧上与第二材料接合。在绝缘体层与第二材料结合之后，在绝缘体层的与绝缘体层的第一侧相对的第二侧上形成集成电路器件。集成电路器件进行热退火。第一种材料在退火过程中保持衬底的第一面的第二结晶状态。

9. 发明申请

US20150194416A1 SINGLE-CHIP FIELD EFFECT TRANSISTOR (FET) SWITCH WITH SILICON GERMANIUM (SiGe) POWER AMPLIFIER AND METHODS OF FORMING 有权
标题翻译：具有硅锗（SiGe）功率放大器的单芯片场效应晶体管（FET）开关及其形成方法
公开(公告)号：US20150194416A1
公开(公告)日：2015-07-09
申请号：US14147186
申请日：2014-01-03
申请人： International Business Machines Corporation
发明人： Peng Cheng , James S. Dunn , Blaine J. Gross , Qizhi Liu , James A. Slinkman
IPC分类号： H01L27/02 , H01L21/02 , H01L29/78 , H01L29/66
CPC分类号： H01L27/1203 , H01L21/3081 , H01L21/764 , H01L27/0207 , H01L27/088 , H01L27/1207 , H01L29/0649 , H01L29/165 , H01L29/456 , H01L29/66477 , H01L29/78 , H01L29/7842
摘要： Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.
摘要翻译：各种实施例包括场效应晶体管（FET）以及形成这种FET的方法。一种方法包括：在前体结构中形成第一组开口，其具有：具有晶体方向的硅衬底，所述硅衬底基本上与第一氧化物邻接; 覆盖硅衬底的硅锗（SiGe）层; 覆盖SiGe层的硅层; 覆盖硅层的第二氧化物; 以及覆盖所述第二氧化物的牺牲层，其中所述第一组开口各自暴露所述硅衬底; 底切在与硅衬底的晶体方向垂直的方向上蚀刻硅衬底以形成与第一组开口对应的沟槽; 钝化第一组开口中的SiGe层或硅层中的至少一个的暴露表面; 并且用电介质至少部分地填充每个沟槽。

10. 发明授权

US08564067B2 Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure 有权
标题翻译：配置为减少谐波的绝缘体上硅（SOI）结构和形成结构的方法
公开(公告)号：US08564067B2
公开(公告)日：2013-10-22
申请号：US13772402
申请日：2013-02-21
申请人： International Business Machines Corporation
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L21/70
CPC分类号： H01L21/02488 , H01L21/2652 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.
摘要翻译：公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。本文还公开了用于形成这种半导体结构的方法的实施例。

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