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1. 发明授权

US09820248B2 Network clock synchronization 有权
公开(公告)号：US09820248B2
公开(公告)日：2017-11-14
申请号：US14755621
申请日：2015-06-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Qian Hu , Yang Liu , Cheng Wei Song , Kai Yang
IPC分类号： H04J3/06 , H04W56/00 , H04L1/00
CPC分类号： H04W56/0015 , H04L1/004 , H04L1/0041
摘要： According to example embodiments of the present invention, predetermined patterns are inserted into data streams and exchanged between a master node and a slave node. By recognizing the patterns near the underlying interface of the physical layer, the master node and slave node can generate timestamps that exactly identify when the respective messages leaves and/or arrives at the physical layer. The slave clock can be synchronized to the master clock based on such timestamps.

2. 发明授权

US08988963B2 Intermediate circuit and method for dram 有权
标题翻译：中级电路和方法
公开(公告)号：US08988963B2
公开(公告)日：2015-03-24
申请号：US14038890
申请日：2013-09-27
申请人： International Business Machines Corporation
发明人： Qian Hu , Yu fei Li , Hao Yang , Wei Wei
IPC分类号： G11C8/00 , G06F13/00 , G11C11/406
CPC分类号： G11C11/406 , G11C11/40611
摘要： An intermediate circuit and method for hiding refresh confliction. The intermediate circuit includes: a first control circuit configured to generate a Command Output Enable signal CON, a Data Read Enable signal DRN and a Refresh Enable signal REFN based on the second clock, wherein a ration of duration the signal CON is in a first state to duration in a second state equals to CLK2/(CLK1-CLK2), the signal REFN has a state that is reverse to that of the signal CON and is used to refresh the DRAM; a command buffer configured to store the access commands received from the user interface and output the stored access commands to the DRAM in response to the first state of the signal CON; a data buffer configured to read data from the DRAM in response to the first state of the signal CON and output the read data.
摘要翻译：一种用于隐藏刷新冲突的中间电路和方法。中间电路包括：第一控制电路，被配置为基于第二时钟产生命令输出使能信号CON，数据读使能信号DRN和刷新使能信号REFN，其中信号CON处于第一状态的持续时间在第二状态下持续时间等于CLK2 /（CLK1-CLK2），信号REFN具有与信号CON相反的状态，并用于刷新DRAM; 命令缓冲器，被配置为存储从用户接口接收的访问命令，并响应于信号CON的第一状态将存储的访问命令输出到DRAM; 数据缓冲器，被配置为响应于信号CON的第一状态从DRAM读取数据并输出读取的数据。

3. 发明申请

US20140092699A1 INTERMEDIATE CIRCUIT AND METHOD FOR DRAM 有权
标题翻译： DRAM的中间电路和方法
公开(公告)号：US20140092699A1
公开(公告)日：2014-04-03
申请号：US14038890
申请日：2013-09-27
申请人： International Business Machines Corporation
发明人： Qian Hu , Yu fei Li , Hao Yang , Wei Wei
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40611
摘要： An intermediate circuit and method for hiding refresh confliction. The intermediate circuit includes: a first control circuit configured to generate a Command Output Enable signal CON, a Data Read Enable signal DRN and a Refresh Enable signal REFN based on the second clock, wherein a ration of duration the signal CON is in a first state to duration in a second state equals to CLK2/(CLK1-CLK2), the signal REFN has a state that is reverse to that of the signal CON and is used to refresh the DRAM; a command buffer configured to store the access commands received from the user interface and output the stored access commands to the DRAM in response to the first state of the signal CON; a data buffer configured to read data from the DRAM in response to the first state of the signal CON and output the read data.
摘要翻译：一种用于隐藏刷新冲突的中间电路和方法。中间电路包括：第一控制电路，被配置为基于第二时钟产生命令输出使能信号CON，数据读使能信号DRN和刷新使能信号REFN，其中信号CON处于第一状态的持续时间在第二状态下持续时间等于CLK2 /（CLK1-CLK2），信号REFN具有与信号CON相反的状态，并用于刷新DRAM; 命令缓冲器，被配置为存储从用户接口接收的访问命令，并响应于信号CON的第一状态将存储的访问命令输出到DRAM; 数据缓冲器，被配置为响应于信号CON的第一状态从DRAM读取数据并输出读取的数据。

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