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1. 发明授权

US11308390B2 Methods and systems of neuron leaky integrate and fire circuits 有权
公开(公告)号：US11308390B2
公开(公告)日：2022-04-19
申请号：US16583308
申请日：2019-09-26
申请人： International Business Machines Corporation
发明人： Mark B. Ritter , Takeo Yasuda
IPC分类号： G06N3/063 , G06N3/04
摘要： Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.

2. 发明申请

US20210241086A1 PERFORMANCE AND AREA EFFICIENT SYNAPSE MEMORY CELL STRUCTURE 有权
公开(公告)号：US20210241086A1
公开(公告)日：2021-08-05
申请号：US16782758
申请日：2020-02-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Takeo Yasuda , Kohji Hosokawa , Junka Okazawa , Akiyo Iwashina
IPC分类号： G06N3/063
摘要： A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.

3. 发明授权

US10552731B2 Digital STDP synapse and LIF neuron-based neuromorphic system 有权
公开(公告)号：US10552731B2
公开(公告)日：2020-02-04
申请号：US14980505
申请日：2015-12-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Takeo Yasuda , Kohji Hosokawa , Yutaka Nakamura , Junka Okazawa , Masatoshi Ishii
IPC分类号： G06N3/063
摘要： Described is a neuromorphic system implemented in hardware that implements neuron membrane potential update based on the leaky integrate and fire (LIF) model. The system further models synapse weights update based on the spike time-dependent plasticity (STDP) model. The system includes an artificial neural network in which the update scheme of neuron membrane potential and synapse weight are effectively defined and implemented.

4. 发明申请

US20190228292A1 SYNAPSE MEMORY 审中-公开
公开(公告)号：US20190228292A1
公开(公告)日：2019-07-25
申请号：US15878965
申请日：2018-01-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Takeo Yasuda , Kohji Hosokawa
IPC分类号： G06N3/063 , G06N3/04 , G11C11/16
摘要： A synapse memory and a method for reading a weight value stored in a synapse memory are provided. The synapse memory includes a memory device configured to store a weight value. The memory device includes a read terminal, a write terminal, and a common terminal, the read terminal being configured to receive a read signal, the write terminal being configured to receive a write signal, and the common terminal being configured to output an output signal from the memory device. The synapse memory also includes a write transistor provided between the write terminal of the memory device and a write signal line configured to send the write signal. The synapse memory further includes a common transistor provided between the common terminal of the memory device and one of the dendrite lines.

5. 发明申请

US20180130528A1 MEMORY CELL STRUCTURE 审中-公开
公开(公告)号：US20180130528A1
公开(公告)日：2018-05-10
申请号：US15346841
申请日：2016-11-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kohji Hosokawa , Masatoshi Ishii , Takeo Yasuda
IPC分类号： G11C13/00 , G11C11/4096
CPC分类号： G11C13/0069 , G11C7/1006 , G11C11/4096 , G11C13/004
摘要： A memory cell structure includes a synapse memory cell including plural cell components, each of the plural cell components including a unit cell, plural write lines arranged for writing a synapse state to the synapse memory cell, each of the plural write lines being used for writing one of a first set of a predetermined number of states to a corresponding cell component by writing one of a second set of the predetermined number of states to the unit cell included in the corresponding cell component, the first set depending on the second set and a number of the unit cell included in the corresponding cell component, and a read line arranged for reading the synapse state from the synapse memory cell, the read line being used for reading one of the first set of the predetermined number of states from all of the plural cell components simultaneously.

6. 发明申请

US20170185889A1 LUT BASED SYNAPSE WEIGHT UPDATE SCHEME IN STDP NEUROMORPHIC SYSTEMS 审中-公开
公开(公告)号：US20170185889A1
公开(公告)日：2017-06-29
申请号：US14980554
申请日：2015-12-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kohji Hosokawa , Masatoshi Ishii , Yutaka Nakamura , Junka Okazawa , Takeo Yasuda
IPC分类号： G06N3/063 , G06N3/08
CPC分类号： G06N3/063 , G06N3/049
摘要： A method and system are provided for updating synapse weight values in neuromorphic system with Spike Time Dependent Plasticity model. The method includes selectively performing, by a hardware-based synapse weight incrementer or decrementer, one of a synapse weight increment function or decrement function, each using a respective lookup table, to generate updated synapse weight values responsive to spike timing data. The method further includes storing the updated synapse weight values in a memory. The method additionally includes performing, by a hardware-based processor, a learning process to integrate the updated synapse weight values stored in the memory into the Spike Time Dependent Plasticity model neuromorphic system for improved neuromorphic simulation.

7. 发明申请

US20170047911A1 PULSE GENERATOR WITH SWITCHED CAPACITORS 审中-公开
标题翻译：脉冲发生器与开关电容器
公开(公告)号：US20170047911A1
公开(公告)日：2017-02-16
申请号：US14949338
申请日：2015-11-23
申请人： International Business Machines Corporation
发明人： Kohji Hosokawa , Masatoshi Ishii , Mark B. Ritter , Takeo Yasuda
IPC分类号： H03K3/356 , H01L49/02
CPC分类号： H03K3/356 , H01L28/40 , H03K4/023
摘要： A pulse generator and a method of fabricating a pulse generator are described. The pulse generator includes an input node to receive an input voltage, a first capacitor, and a second capacitor. The first capacitor is positioned between the input node and the second capacitor. An output node outputs an output voltage with a pulse shape, and the pulse generator also includes at least one switch between the input node and the second capacitor. The at least one switch controls the pulse shape of the output voltage.
摘要翻译：描述脉冲发生器和制造脉冲发生器的方法。脉冲发生器包括用于接收输入电压的输入节点，第一电容器和第二电容器。第一电容器位于输入节点和第二电容器之间。输出节点输出具有脉冲形状的输出电压，脉冲发生器还包括输入节点和第二电容器之间的至少一个开关。至少一个开关控制输出电压的脉冲形状。

8. 发明授权

US08717836B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08717836B2
公开(公告)日：2014-05-06
申请号：US13653701
申请日：2012-10-17
申请人： International Business Machines Corporation
发明人： Takeo Yasuda
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C8/08 , G11C8/10 , G11C8/18
摘要： A Static Random Access Memory (SRAM) includes word lines WL, bit lines BL, address decoders that select one of the word lines WL in response to an address signal AD, a sense amplifier that is activated in response to a sense amplifier enable signal SAE, and a sense amplifier control circuit that generates the sense amplifier enable signal SAE. In this device, the more distant the word line WL is from the sense amplifier, the longer the sense amplifier control circuit sets the delay time of the sense amplifier enable signal SAE so that the more distant the word line WL is from the sense amplifier, the later the sense amplifier is activated.
摘要翻译：静态随机存取存储器（SRAM）包括字线WL，位线BL，响应于地址信号AD选择字线WL之一的地址解码器，响应于读出放大器使能信号SAE而被激活的读出放大器以及产生读出放大器使能信号SAE的读出放大器控制电路。在该装置中，字线WL距离读出放大器越远，读出放大器控制电路设置读出放大器使能信号SAE的延迟时间越长，使得字线WL越远离读出放大器，感测放大器后来激活。

9. 发明申请

US20230076654A1 SYNAPSE MEMORY 有权
公开(公告)号：US20230076654A1
公开(公告)日：2023-03-09
申请号：US17988089
申请日：2022-11-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Takeo Yasuda , Kohji Hosokawa
IPC分类号： G06N3/063 , G11C11/16 , G06N3/04 , G11C11/54
摘要： A synapse memory and a method for reading a weight value stored in a synapse memory are provided. The synapse memory includes a memory device configured to store a weight value. The memory device includes a read terminal, a write terminal, and a common terminal, the read terminal being configured to receive a read signal, the write terminal being configured to receive a write signal, and the common terminal being configured to output an output signal from the memory device. The synapse memory also includes a write transistor provided between the write terminal of the memory device and a write signal line configured to send the write signal. The synapse memory further includes a common transistor provided between the common terminal of the memory device and one of the dendrite lines.

10. 发明申请

US20210225439A1 SYNAPSE WEIGHT UPDATE COMPENSATION 有权
公开(公告)号：US20210225439A1
公开(公告)日：2021-07-22
申请号：US16744762
申请日：2020-01-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Takeo Yasuda , Atsuya Okazaki
IPC分类号： G11C11/54 , G11C11/56 , G11C11/409 , H03K19/17728 , G06N3/063
摘要： A synapse memory system includes synapse memory cells, each of which includes a non-volatile random access memory (NVRAM). Each synapse memory cell is configured to store a weight value according to an output level of a write signal. A write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell. The output controller is configured to control the output level of the write signal of the write driver. Read drivers are configured to read the weight value stored in the synapse memory cells. The output controller is configured to control the output level of the write signal in updating the weight value in the synapse memory cell, to compensate for weight value variation according to a device characteristic of the NVRAM.

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