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1. 发明申请

US20230034968A1 Tile Assignment to Processing Cores Within a Graphics Processing Unit 有权
公开(公告)号：US20230034968A1
公开(公告)日：2023-02-02
申请号：US17965652
申请日：2022-10-13
申请人： Imagination Technologies Limited
发明人： Rudi Bonfiglioli , Richard Broadhurst
IPC分类号： G06T1/20 , G06F9/38 , G06T15/00 , G06T17/10
摘要： A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising: a plurality of processing cores configured to render graphics data; cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles; similarity indication logic configured to obtain similarity indications between sets of one or more tiles of the rendering space, wherein the similarity indication between two sets of one or more tiles is indicative of a level of similarity between the two sets of tiles according to at least one processing metric; and scheduling logic configured to assign the sets of one or more tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications.

2. 发明申请

US20220262061A1 GRAPHICS PROCESSING UNITS AND METHODS FOR CONTROLLING RENDERING COMPLEXITY USING COST INDICATIONS FOR SETS OF TILES OF A RENDERING SPACE 有权
公开(公告)号：US20220262061A1
公开(公告)日：2022-08-18
申请号：US17735932
申请日：2022-05-03
申请人： Imagination Technologies Limited
发明人： John W. Howson , Richard Broadhurst , Steven Fishwick
IPC分类号： G06T15/00 , G06T17/10 , G06T15/40 , G06T15/04 , G06T15/06 , G06T15/80 , G06T11/40
摘要： A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.

3. 发明申请

US20210327124A1 USING TILING DEPTH INFORMATION IN HIDDEN SURFACE REMOVAL IN A GRAPHICS PROCESSING SYSTEM 有权
公开(公告)号：US20210327124A1
公开(公告)日：2021-10-21
申请号：US17364096
申请日：2021-06-30
申请人： Imagination Technologies Limited
发明人： Richard Broadhurst , John Howson , Robert Theed
IPC分类号： G06T15/40 , G06T15/00
摘要： A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitives, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will subsequently be hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.

4. 发明申请

US20210090317A1 GRAPHICS PROCESSING UNITS AND METHODS FOR CONTROLLING RENDERING COMPLEXITY USING COST INDICATIONS FOR SETS OF TILES OF A RENDERING SPACE 有权
公开(公告)号：US20210090317A1
公开(公告)日：2021-03-25
申请号：US17111317
申请日：2020-12-03
申请人： Imagination Technologies Limited
发明人： John W. Howson , Richard Broadhurst , Steven Fishwick
IPC分类号： G06T15/00 , G06T17/10 , G06T15/40 , G06T15/04 , G06T15/06 , G06T15/80 , G06T11/40
摘要： A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.

5. 发明申请

US20200264808A1 Allocation of Memory 审中-公开
公开(公告)号：US20200264808A1
公开(公告)日：2020-08-20
申请号：US16791433
申请日：2020-02-14
申请人： Imagination Technologies Limited
发明人： Isuru Herath , Richard Broadhurst
IPC分类号： G06F3/06
摘要： Methods of memory allocation map registers referenced by different groups of instances of the same task to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.

6. 发明授权

US10140761B2 Generation of a control stream for a tile 有权
公开(公告)号：US10140761B2
公开(公告)日：2018-11-27
申请号：US15499038
申请日：2017-04-27
申请人： Imagination Technologies Limited
发明人： Xile Yang , Lorenzo Belli , Richard Broadhurst
IPC分类号： G06T15/00 , G06T17/20 , G06T17/10 , G06T11/40
摘要： A method of processing primitives within a tiling unit of a graphics processing system comprises determining whether a primitive falls within a tile based on positions of samples within each pixel. If it is determined that the primitive does fall within a tile based on the positions of samples within pixels in a tile, an association between the tile and the primitive is stored to indicate that the primitive is present in the tile. For example, an identifier for the primitive may be added to a control stream for the tile to indicate that the primitive is present in the tile. Various different methods are described to make the determination and these may be used separately or in any combination.

7. 发明申请

US20160098856A1 USING TILING DEPTH INFORMATION IN HIDDEN SURFACE REMOVAL IN A GRAPHICS PROCESSING SYSTEM 审中-公开
标题翻译：在图形处理系统中使用倾斜表面去除的倾斜深度信息
公开(公告)号：US20160098856A1
公开(公告)日：2016-04-07
申请号：US14875873
申请日：2015-10-06
申请人： Imagination Technologies Limited
发明人： Richard Broadhurst , John Howson , Robert Theed
IPC分类号： G06T15/40 , G06T1/20
CPC分类号： G06T15/405 , G06T15/005
摘要： A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitive fragments, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will be subsequently hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.
摘要翻译：图形处理系统包括用于执行平铺计算的平铺单元和用于在基元的片段上执行HSR的隐藏表面去除（HSR）单元。原始深度信息在平铺单元中计算并转发以供HSR单元在片段上执行HSR。这利用了在HSR单元在原始片段上执行HSR之前访问原始数据的拼接单元，以确定可以简化由HSR单元执行的HSR的一些深度信息。因此，可以在HSR单元中使用在平铺单元中确定的深度缓冲器的最终值，以确定特定片段随后将被HSR单元中尚未被处理的原语的片段隐藏，使得可以剔除特定片段。

8. 发明申请

US20220269527A1 Task Repacking 有权
公开(公告)号：US20220269527A1
公开(公告)日：2022-08-25
申请号：US17678335
申请日：2022-02-23
申请人： Imagination Technologies Limited
发明人： Panagiotis Velentzas , John W. Howson , Richard Broadhurst
IPC分类号： G06F9/48
摘要： A method of repacking tasks in a graphics pipeline includes, in response to a task reaching a checkpoint in a program, determining if the task is eligible for repacking. If the task is eligible for repacking, the task is de-scheduled and it is determined whether repacking conditions are satisfied. In the event that the repacking conditions are satisfied, the method looks for a pair of compatible and non-conflicting tasks at the checkpoint. If such a pair of tasks are found, one or more instances are transferred between the pair of tasks.

9. 发明授权

US11348302B2 Graphics processing units and methods for controlling rendering complexity using cost indications for sets of tiles of a rendering space 有权
公开(公告)号：US11348302B2
公开(公告)日：2022-05-31
申请号：US17111317
申请日：2020-12-03
申请人： Imagination Technologies Limited
发明人： John W. Howson , Richard Broadhurst , Steven Fishwick
IPC分类号： G06T15/00 , G06T17/10 , G06T15/40 , G06T15/04 , G06T15/06 , G06T15/80 , G06T11/40 , G06F9/38
摘要： A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.

10. 发明申请

US20220012841A1 Task Merging 有权
公开(公告)号：US20220012841A1
公开(公告)日：2022-01-13
申请号：US17333695
申请日：2021-05-28
申请人： Imagination Technologies Limited
发明人： Roger Hernando Buch , Panagiotis Velentzas , Richard Broadhurst , Xile Yang , John W. Howson
IPC分类号： G06T1/20 , G06T1/60 , G06F9/48 , G06F9/50 , G06F9/52 , G06F12/02
摘要： Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.

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