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1. 发明授权

US11600034B2 Methods and control stream generators for generating a control stream for a tile group in a graphics processing system 有权
公开(公告)号：US11600034B2
公开(公告)日：2023-03-07
申请号：US17170590
申请日：2021-02-08
申请人： Imagination Technologies Limited
发明人： Diego Jesus , John W. Howson , Panagiotis Velentzas , Robert Brigg , Xile Yang
IPC分类号： G06T15/00 , G06T1/20 , G06T1/60 , G06T11/40 , G06T9/00 , G06T11/20 , G06T15/04 , G06T17/10
摘要： Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group. The method includes: receiving information identifying one or more primitive blocks relevant to rendering at least one tile in the tile group, each primitive block comprising one or more primitives; generating a primitive block entry for each of the identified primitive blocks; and adding each primitive block entry to the control stream; wherein generating the primitive block entry for at least one of the identified primitive blocks comprises: (i) identifying a bounding box encompassing the one or more primitives of the primitive block; (ii) generating a coverage mask that indicates which tiles of the tile group that intersect the bounding box for the primitive block are valid for the primitive block, a tile being valid for a primitive block if at least one primitive of the primitive blocks falls, at least partially, within the bounds of the tile; and (iii) including the coverage mask in the primitive block entry.

2. 发明授权

US11244421B2 Memory for storing untransformed primitive blocks 有权
公开(公告)号：US11244421B2
公开(公告)日：2022-02-08
申请号：US16775981
申请日：2020-01-29
申请人： Imagination Technologies Limited
发明人： Robert Brigg
IPC分类号： G06T1/20 , G06T1/60 , G06F9/30 , G06T17/10 , G06T15/00
摘要： Memories and methods for storing untransformed primitive blocks of variable size in a memory structure of a graphics processing system, the untransformed primitive blocks having been generated by geometry processing logic of the graphics processing system. The method includes: storing an untransformed primitive block in the memory structure, and increasing, by a predetermined amount, a current total amount of memory allocated for storing untransformed primitive blocks; determining an unused amount of the current total amount of memory allocated for storing untransformed primitive blocks; receiving a new untransformed primitive block for storing in the memory structure, and determining whether a size of the new untransformed primitive block is less than or equal to the unused amount; and if it is determined that the size of the new untransformed primitive block is less than or equal to the unused amount, storing the new untransformed primitive block in the memory structure.

3. 发明申请

US20210383598A1 Transformed Geometry Data Cache for Graphics Processing Systems 有权
公开(公告)号：US20210383598A1
公开(公告)日：2021-12-09
申请号：US17407719
申请日：2021-08-20
申请人： Imagination Technologies Limited
发明人： Robert Brigg , John W. Howson , Xile Yang
IPC分类号： G06T15/40 , G06T15/00 , G06T1/60
摘要： A cache for use in a tile-based rendering graphics processing system for storing transformed primitive blocks, the graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated, the graphics processing system comprising rasterization logic that rasterizes primitives on a per tile basis in a plurality of stages, the cache comprising: memory configured to store a plurality of transformed primitive blocks in the cache, each transformed primitive block comprising transformed geometry data for one or more primitives; control logic configured to: maintain a counter for each of the plurality of transformed primitive blocks stored in the cache that indicates a number of tiles of the plurality of tiles that are currently being processed by the rasterization logic and require access to that transformed primitive block, the counter being updated when any stage of the rasterization logic indicates a tile no longer requires access to the transformed primitive block; in response to receiving a request to add a new transformed primitive block to the cache when the cache is full, select a transformed primitive block to evict from the cache based on the counters associated therewith; and evict the selected transformed primitive block from the cache.

4. 发明申请

US20210295591A1 PRIMITIVE FRAGMENT PROCESSING IN THE RASTERIZATION PHASE OF A GRAPHICS PROCESSING SYSTEM 有权
公开(公告)号：US20210295591A1
公开(公告)日：2021-09-23
申请号：US17331537
申请日：2021-05-26
申请人： Imagination Technologies Limited
发明人： Robert Brigg , Lorenzo Belli
IPC分类号： G06T15/40 , G06F7/24 , G06F9/48 , G06T1/60 , G06T17/10 , G06T7/50 , G06T15/20
摘要： Systems and methods for processing primitive fragments in a rasterization phase of a graphics processing system wherein a rendering space is subdivided into a plurality of tiles. The method includes receiving a plurality of primitive fragments, each primitive fragment corresponding to a pixel sample in a tile; determining whether a depth buffer read is to be performed for hidden surface removal processing of one or more of the primitive fragments; sorting the primitive fragments into a priority queue and a non-priority queue based on the depth buffer read determinations; and performing hidden surface removal processing on the primitive fragments in the priority and non-priority queues wherein priority is given to the primitive fragments in the priority queue.

5. 发明申请

US20210110510A1 HIERARCHICAL TILING IN A GRAPHICS PROCESSING SYSTEM USING CHAIN SORTING OF PRIMITIVES 有权
公开(公告)号：US20210110510A1
公开(公告)日：2021-04-15
申请号：US17026506
申请日：2020-09-21
申请人： Imagination Technologies Limited
发明人： Robert Brigg , Lorenzo Belli
IPC分类号： G06T1/60 , G06T1/20 , G06T15/00
摘要： Tiling engines and methods for use in a graphics processing system for hierarchically tiling a plurality of primitives. The tiling engine includes: a chain of sorting units comprising a top level sorting unit followed by one or more lower level sorting units, wherein: the top level sorting unit is configured to: determine which of a plurality of regions of a render space each of the plurality of primitives, at least partially, falls within; and for each region a primitive, at least partially, falls within, store an identifier of that primitive in a queue of the top level sorting unit that is associated with that region; and each of the one or more lower level sorting units is configured to: select one or more queues of a preceding sorting unit in the chain to process; for each of the selected queues, determine which of a plurality of sub-regions of the region associated with that queue each of the primitives identified in that queue, at least partially, falls within; and for each sub-region a primitive, at least partially, falls within, store an identifier of that primitive in a queue of the lower level sorting unit that is associated with that sub-region; and an output unit configured to output the primitives identified in the queues of the last lower level sorting unit in the chain on a queue by queue basis.

6. 发明公开

US20240135625A1 DATA STRUCTURES, METHODS AND TILING ENGINES FOR STORING TILING INFORMATION IN A GRAPHICS PROCESSING SYSTEM 审中-公开
公开(公告)号：US20240135625A1
公开(公告)日：2024-04-25
申请号：US18401566
申请日：2023-12-31
申请人： Imagination Technologies Limited
发明人： Xile Yang , Robert Brigg , Michael John Livesley
IPC分类号： G06T15/00 , G06T1/20 , G06T1/60
CPC分类号： G06T15/005 , G06T1/20 , G06T1/60 , G06T2210/52
摘要： Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block. A tile is a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile.

7. 发明授权

US11836849B2 Primitive block generator for graphics processing systems 有权
公开(公告)号：US11836849B2
公开(公告)日：2023-12-05
申请号：US18071095
申请日：2022-11-29
申请人： Imagination Technologies Limited
发明人： Xile Yang , Robert Brigg , John W. Howson
IPC分类号： G06T15/40 , G06T15/00 , G06T1/60
CPC分类号： G06T15/40 , G06T1/60 , G06T15/005
摘要： Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods comprise: receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.

8. 发明公开

US20230260074A1 Graphics Processing Systems with Expansion Transformation Stage Masks 审中-公开
公开(公告)号：US20230260074A1
公开(公告)日：2023-08-17
申请号：US18140554
申请日：2023-04-27
申请人： Imagination Technologies Limited
发明人： Robert Brigg , John Howson , Xile Yang
IPC分类号： G06T1/60 , G06F9/30 , G06T1/20 , G06T17/10 , G06T15/00
CPC分类号： G06T1/60 , G06F9/30018 , G06F9/30029 , G06F9/30145 , G06T1/20 , G06T17/10 , G06T15/005
摘要： A graphics processing system for generating a rendering output includes geometry processing logic having first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block used in generating the rendering output. Rasterization logic includes second transformation logic configured to re-transform the plurality of untransformed primitives into the plurality of transformed primitives on an untransformed primitive block-basis in accordance with the expansion transformation stage mask for the one or more expansion transformation stages; and logic configured to render the transformed primitives to generate the rendering output.

9. 发明公开

US20230252711A1 METHODS AND CONTROL STREAM GENERATORS FOR GENERATING A CONTROL STREAM FOR A TILE GROUP IN A GRAPHICS PROCESSING SYSTEM 审中-公开
公开(公告)号：US20230252711A1
公开(公告)日：2023-08-10
申请号：US18118262
申请日：2023-03-07
申请人： Imagination Technologies Limited
发明人： Diego Jesus , John W. Howson , Panagiotis Velentzas , Robert Brigg , Xile Yang
IPC分类号： G06T15/00 , G06T1/20 , G06T9/00 , G06T15/04 , G06T17/10 , G06T11/20 , G06T11/40 , G06T1/60
CPC分类号： G06T15/005 , G06T1/20 , G06T1/60 , G06T9/00 , G06T11/20 , G06T11/40 , G06T15/00 , G06T15/04 , G06T17/10 , G06T2210/12
摘要： Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group. Information is received identifying one or more primitive blocks relevant to rendering at least one tile in the tile group, each primitive block comprising one or more primitives; generating a primitive block entry for each of the identified primitive blocks; and adding each primitive block entry to the control stream; wherein generating the primitive block entry for at least one of the identified primitive blocks comprises: (i) identifying a bounding box encompassing the one or more primitives of the primitive block; (ii) generating a coverage mask that indicates which tiles of the tile group that intersect the bounding box for the primitive block are valid for the primitive block, a tile being valid for a primitive block if at least one primitive of the primitive blocks falls, at least partially, within the bounds of the tile; and (iii) including the coverage mask in the primitive block entry.

10. 发明授权

US11699258B2 Graphics processing method and system for rendering items of geometry based on their size 有权
公开(公告)号：US11699258B2
公开(公告)日：2023-07-11
申请号：US17169607
申请日：2021-02-08
申请人： Imagination Technologies Limited
发明人： Xile Yang , Robert Brigg
IPC分类号： G06T15/00 , G06T11/20 , G06T15/04 , G06T11/40 , G06T7/13 , G06T1/20
CPC分类号： G06T15/005 , G06T1/20 , G06T7/13 , G06T11/20 , G06T11/40 , G06T15/00 , G06T15/04 , G06T2210/12
摘要： Methods and graphics processing systems render primitives using a rendering space which is subdivided into a plurality of regions. Geometry processing logic performs a geometry processing phase which determines, for each of a plurality of primitives which are present in a region, whether the primitive totally covers the region; and stores data for the primitives which are present in the region, wherein the stored data comprises, for each of the primitives which are determined to totally cover the region, data to indicate total coverage of the region. Rendering logic performs a rendering phase for rendering primitives within the region. The rendering phase retrieves the stored data for the primitives which are present in the region; selectively processes the primitives which are present in the region based on the retrieved data to determine which sample points within the region are covered by the primitives, wherein if the retrieved data includes data which indicates total coverage of the region for a particular primitive then the processing determines which sample points within the region are covered by the particular primitive is skipped; and determines rendered values at the sample points within the region based on the primitives which cover the respective sample points.

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