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1. 发明申请

US20230051100A1 SEMICONDUCTOR PACKAGE HAVING A LEAD FRAME AND A CLIP FRAME 有权
公开(公告)号：US20230051100A1
公开(公告)日：2023-02-16
申请号：US17980004
申请日：2022-11-03
申请人： Infineon Technologies AG
发明人： Bun Kian Tay , Mei Yih Goh , Martin Gruber , Josef Hoeglauer , Michael Juerss , Josef Maerz , Thorsten Meyer , Thorsten Scharf , Chee Voon Tan
IPC分类号： H01L23/498 , H01L23/31 , H01L21/56 , H01L23/495 , H01L21/48
摘要： A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

2. 发明授权

US11302613B2 Double-sided cooled molded semiconductor package 有权
公开(公告)号：US11302613B2
公开(公告)日：2022-04-12
申请号：US16924851
申请日：2020-07-09
申请人： Infineon Technologies AG
发明人： Chau Fatt Chiang , Swee Kah Lee , Josef Maerz , Thomas Stoek , Chee Voon Tan
IPC分类号： H01L23/495 , H01L23/31 , H01L21/56 , H01L21/48 , H01L23/18
摘要： A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.

3. 发明公开

US20230282553A1 POWER ELECTRONIC ASSEMBLY AND POWER MODULE FOR EMBEDDING IN A PRINTED CIRCUIT BOARD 审中-公开
公开(公告)号：US20230282553A1
公开(公告)日：2023-09-07
申请号：US18315787
申请日：2023-05-11
申请人： Infineon Technologies AG
发明人： Thomas Stoek , Frank Daeche , Chee Voon Tan
IPC分类号： H01L23/495 , H01L23/00 , H01L21/48 , H05K1/18
CPC分类号： H01L23/49537 , H01L23/49524 , H01L24/33 , H01L21/4842 , H01L24/97 , H01L24/83 , H05K1/185 , H01L21/4825 , H01L2224/83385 , H01L23/49513 , H01L24/32 , H01L2224/32245 , H01L2224/33181 , H01L24/05 , H01L2224/05647 , H01L24/06 , H01L2224/06181 , H01L2224/83815 , H01L2224/83203 , H05K3/0035
摘要： A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/−30 μm at the first side of the power module.

4. 发明授权

US11211356B2 Power semiconductor package and method for fabricating a power semiconductor package 有权
公开(公告)号：US11211356B2
公开(公告)日：2021-12-28
申请号：US16991123
申请日：2020-08-12
申请人： Infineon Technologies AG
发明人： Wee Aun Jason Lim , Paul Armand Asentista Calo , Ting Soon Chin , Chooi Mei Chong , Sanjay Kumar Murugan , Ying Pok Sam , Chee Voon Tan
IPC分类号： H01L23/495 , H01L23/28 , H01L21/00 , H05K7/18 , H01L23/00 , H01L21/56 , H01L23/31 , H01L23/498
摘要： A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

5. 发明申请

US20210366732A1 Semiconductor Package with Lead Tip Inspection Feature 有权
公开(公告)号：US20210366732A1
公开(公告)日：2021-11-25
申请号：US16882008
申请日：2020-05-22
申请人： Infineon Technologies AG
发明人： Chau Fatt Chiang , Khay Chwan Andrew Saw , Chee Voon Tan
IPC分类号： H01L21/56 , H01L21/78 , H01L23/31 , H01L23/48 , H01L23/538
摘要： A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices the sidewall-facing terminal is electrically connected to the semiconductor die of the respective packaged semiconductor device. The sidewall-facing terminal of each packaged semiconductor device is provided from the electrically conductive material formed within the gaps.

6. 发明授权

US10886199B1 Molded semiconductor package with double-sided cooling 有权
公开(公告)号：US10886199B1
公开(公告)日：2021-01-05
申请号：US16514115
申请日：2019-07-17
申请人： Infineon Technologies AG
发明人： Chau Fatt Chiang , Swee Kah Lee , Josef Maerz , Thomas Stoek , Chee Voon Tan
IPC分类号： H01L23/495 , H01L23/31 , H01L23/29 , H01L21/56 , H01L23/18
摘要： A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.

7. 发明申请

US20210057375A1 Power Semiconductor Package and Method for Fabricating a Power Semiconductor Package 有权
公开(公告)号：US20210057375A1
公开(公告)日：2021-02-25
申请号：US16991123
申请日：2020-08-12
申请人： Infineon Technologies AG
发明人： Wee Aun Jason Lim , Paul Armand Asentista Calo , Ting Soon Chin , Chooi Mei Chong , Sanjay Kumar Murugan , Ying Pok Sam , Chee Voon Tan
IPC分类号： H01L23/00 , H01L21/56 , H01L23/31 , H01L23/495
摘要： A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

8. 发明申请

US20210020547A1 Molded Semiconductor Package with Double-Sided Cooling 有权
公开(公告)号：US20210020547A1
公开(公告)日：2021-01-21
申请号：US16514115
申请日：2019-07-17
申请人： Infineon Technologies AG
发明人： Chau Fatt Chiang , Swee Kah Lee , Josef Maerz , Thomas Stoek , Chee Voon Tan
IPC分类号： H01L23/495 , H01L23/31 , H01L21/56 , H01L23/29
摘要： A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.

9. 发明申请

US20150249067A1 Semiconductor Device Having Multiple Chips Mounted to a Carrier 有权
标题翻译：具有安装到载体的多个芯片的半导体器件
公开(公告)号：US20150249067A1
公开(公告)日：2015-09-03
申请号：US14193897
申请日：2014-02-28
申请人： Infineon Technologies AG
发明人： Boon Seong Lee , Chee Voon Tan
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L25/074 , H01L25/50 , H01L2224/0603 , H01L2224/48247 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2225/0651 , H01L2225/06562 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device includes a chip carrier having a first surface and a second surface opposite to the first surface. The device further includes a first semiconductor chip mounted on the first surface of the chip carrier. A second semiconductor chip is mounted on the second surface of the chip carrier, wherein a portion of a first surface of the second semiconductor chip which faces the chip carrier projects over an edge of the chip carrier. A first electrical conductor is coupled to an electrode formed on the portion of the first surface of the second semiconductor chip that projects over the edge of the chip carrier.
摘要翻译：半导体器件包括具有第一表面和与第一表面相对的第二表面的芯片载体。该装置还包括安装在芯片载体的第一表面上的第一半导体芯片。第二半导体芯片安装在芯片载体的第二表面上，其中面向芯片载体的第二半导体芯片的第一表面的一部分突出在芯片载体的边缘上。第一电导体耦合到形成在第二半导体芯片的第一表面的在芯片载体的边缘上突出的部分上的电极。

10. 发明申请

US20150214297A1 ELECTRONIC ARRAY AND CHIP PACKAGE 有权
标题翻译：电子阵列和芯片包装
公开(公告)号：US20150214297A1
公开(公告)日：2015-07-30
申请号：US14166880
申请日：2014-01-29
申请人： Infineon Technologies AG
发明人： Volker Strutz , Horst Theuss , Chee Voon Tan , Hui Teng Wang
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L24/32 , H01L2224/32145 , H01L2224/48091 , H01L2224/73265 , H01L2924/00014 , H01L2224/45099
摘要： An electronic array may include a first electronic component which has a first operation voltage, a second electronic component which has a second operation voltage, wherein the second operation voltage is different from the first operation voltage and wherein the first electronic component and the second electronic component are arranged over each other, an isolation layer between the first electronic component and the second electronic component, wherein the isolation layer electrically isolates the first electronic component from the second electronic component, at least one connection layer formed at least partially between the isolation layer and the first electronic component or between the isolation layer and the second electronic component, wherein the connection layer includes a first portion and a second portion, wherein the first portion and the second portion each extend from the corresponding electronic component to the isolation layer, wherein the first portion includes an electrically isolating material which fixes the isolation layer to the corresponding electronic component and wherein the second portion includes an electrically conductive material which electrically couples the corresponding electronic component to the isolation layer.
摘要翻译：电子阵列可以包括具有第一操作电压的第一电子部件，具有第二操作电压的第二电子部件，其中第二操作电压不同于第一操作电压，并且其中第一电子部件和第二电子部件在第一电子部件和第二电子部件之间布置有隔离层，其中隔离层将第一电子部件与第二电子部件电隔离，至少一个连接层至少部分地形成在隔离层和所述第一电子部件或所述隔离层和所述第二电子部件之间，其中所述连接层包括第一部分和第二部分，其中所述第一部分和所述第二部分各自从相应的电子部件延伸到所述隔离层，其中，第一部分包括a n隔离材料，其将隔离层固定到相应的电子部件，并且其中第二部分包括将相应的电子部件电耦合到隔离层的导电材料。

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