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    • 4. 发明申请
    • CURRENT MEASUREMENT IN A POWER SEMICONDUCTOR ARRANGEMENT
    • 功率半导体装置中的电流测量
    • US20150377931A1
    • 2015-12-31
    • US14320143
    • 2014-06-30
    • Infineon Technologies AG
    • Rainald Sander
    • G01R19/00
    • G01R19/0092G01R31/2607G01R31/2639
    • A semiconductor arrangement may comprise a multiplicity of semiconductor elements with controlling paths and controlled paths, the controlled paths having controllable conductivities and being connected parallel to each other. The semiconductor arrangement may also comprise a current evaluation circuit configured to measure current strengths of currents present in the controlled paths and to provide a signal representing the sum of the measured current strengths, and a control circuit connected to the controlling paths and configured to control the conductivities of the controlled paths in accordance with an input signal and the signal representing the sum of the current strengths, wherein at least one controlled path is controlled to have minimum conductivity if the signal representing the sum of the current strengths is below a threshold value.
    • 半导体布置可以包括具有控制路径和受控路径的多个半导体元件,受控路径具有可控制的导电性并且彼此并联连接。 半导体布置还可以包括电流评估电路,其被配置为测量存在于受控路径中的电流的电流强度,并且提供表示所测量的电流强度之和的信号,以及连接到控制路径并被配置为控制 根据输入信号和表示电流强度之和的信号的受控路径的电导率,其中如果表示电流强度之和的信号低于阈值,则控制至少一个受控路径具有最小的导电性。
    • 5. 发明申请
    • SEMICONDUCTOR PACKAGE AND METHOD FOR PRODUCING A SEMICONDUCTOR PACKAGE
    • US20230131909A1
    • 2023-04-27
    • US18045393
    • 2022-10-10
    • Infineon Technologies AG
    • Rainald SanderLars EckertFortunato Lopez
    • H01L25/16H01L23/00H01L23/495
    • A semiconductor package comprises an encapsulation having a first lateral side and an opposite second lateral side, at least one power semiconductor chip having a drain contact region running along the first lateral side, a source contact region running along the second lateral side, and first and second inner contact regions arranged between the drain and source contact regions, a first external terminal which is connected to the drain contact region, is arranged centrally on the first lateral side, and is configured to apply a supply voltage for the at least one power semiconductor chip, a second external terminal which is connected to the source contact region, is arranged centrally on the second lateral side, and is configured to apply a reference voltage for the at least one power semiconductor chip, third and fourth external terminals which are connected to the first inner contact region. are arranged opposite each other at a first end of the first and second lateral sides, respectively, and are configured a first output of the semiconductor package, and fifth and sixth external terminals which are connected to the second inner contact region and are arranged opposite each other at a second end of the first and second lateral sides, respectively, and are configured as a second output of the semiconductor package.