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1. 发明授权

US11455104B2 Determination of a resultant data word when accessing a memory 有权
公开(公告)号：US11455104B2
公开(公告)日：2022-09-27
申请号：US17144723
申请日：2021-01-08
申请人： Infineon Technologies AG
发明人： Thomas Kern , Michael Goessel
IPC分类号： G11C29/42 , G06F3/06
摘要： Method for determining a resultant data word when accessing memory cells of a memory, comprising the steps: (a) reading a set of memory cells, (b) wherein a first data word and a second data word are determined from the read set of memory cells, wherein each memory cell is assigned a component of the first data word and the corresponding component of the second data word, (c) wherein the first data word and the second data word for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller, (d) wherein the first data word and the second data word for the respective memory cell assume at least one third value if the conditions according to feature (c) are not satisfied, and (e) determining the resultant data word on the basis of the first data word or on the basis of the second data word. A corresponding device is also proposed.

2. 发明授权

US10567007B2 Device and method of processing a data word using checkbits 有权
公开(公告)号：US10567007B2
公开(公告)日：2020-02-18
申请号：US15449029
申请日：2017-03-03
申请人： Infineon Technologies AG
发明人： Thomas Kern , Roland Brachmann , Michael Goessel
IPC分类号： H03M13/29 , G06F11/10
摘要： A method is proposed for processing a data word, in which the data word comprises a first partial data word and a second partial data word, in which first checkbits are defined for the first partial data word, wherein the first partial data word and the first checkbits form a first codeword, in which second checkbits are defined for the second partial data word, wherein the second partial data word and the second checkbits form a second codeword, in which third checkbits are defined for the data word, wherein at least (i) the data word, (ii) a linking of the first checkbits with the second checkbits, and (iii) the third checkbits are parts of a third codeword.

3. 发明授权

US10200065B2 Apparatus and method for correcting at least one bit error within a coded bit sequence 有权
公开(公告)号：US10200065B2
公开(公告)日：2019-02-05
申请号：US13975621
申请日：2013-08-26
申请人： Infineon Technologies AG
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt , Stephane Lacouture
IPC分类号： H03M13/00 , H03M13/15
摘要： An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.

4. 发明授权

US09805771B2 Determining a state of a cell structure 有权
公开(公告)号：US09805771B2
公开(公告)日：2017-10-31
申请号：US14190435
申请日：2014-02-26
申请人： Infineon Technologies AG
发明人： Ulrich Loibl , Thomas Kern
IPC分类号： G11C11/4091 , G11C7/06 , G11C16/34 , G11C29/02 , G11C29/50 , G11C11/16 , G11C13/00 , G11C17/00
CPC分类号： G11C7/06 , G11C7/062 , G11C7/065 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C13/00 , G11C16/349 , G11C17/00 , G11C29/028 , G11C29/50
摘要： A method is suggested for determining a state of a cell structure, wherein the cell structure includes several memory cells, the method includes: (i) detecting a first condition in a predetermined number of memory cells; and (ii) determining the state of the cell structure by assigning a second condition to the memory cells that do not show the first condition.

5. 发明授权

US09672941B1 Memory element status detection 有权
公开(公告)号：US09672941B1
公开(公告)日：2017-06-06
申请号：US15018264
申请日：2016-02-08
申请人： Infineon Technologies AG
发明人： Giacomo Curatolo , Thomas Kern
IPC分类号： G11C7/00 , G11C29/50
CPC分类号： G11C29/50 , G11C7/00 , G11C7/062 , G11C7/067 , G11C7/16 , G11C29/12005 , G11C29/1201 , G11C2029/5004 , G11C2029/5006 , G11C2207/063
摘要： A circuit having a memory element coupled between and having a full voltage between two supply rails; and a detection unit coupled to the memory element and configured to maintain a substantially constant biasing of the memory element while simultaneously detecting current flow through the memory element.

6. 发明授权

US09569354B2 System and method to emulate an electrically erasable programmable read-only memory 有权
标题翻译：用于模拟电可擦除可编程只读存储器的系统和方法
公开(公告)号：US09569354B2
公开(公告)日：2017-02-14
申请号：US13957604
申请日：2013-08-02
申请人： Infineon Technologies AG
发明人： Ulrich Backhausen , Thomas Kern , Thomas Nirschl , Jens Rosenbusch , Xiangting Bi , Edvin Paparisto
IPC分类号： G06F12/02 , G06F11/10 , G11C29/18
CPC分类号： G06F12/0246 , G06F11/1048 , G06F12/0238 , G06F12/0292 , G06F2212/1032 , G06F2212/7201 , G06F2212/7207 , G11C2029/1806
摘要： The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.
摘要翻译：本公开涉及一种电子存储器系统，更具体地，涉及一种用于模拟电可擦除可编程只读存储器的系统，以及用于模拟电可擦除可编程只读存储器的方法。根据本公开的实施例，提供了一种用于模拟电可擦除可编程只读存储器的系统，所述系统包括第一存储器部分和第二存储器部分，其中第一存储器部分包括多个存储位置，其被配置为存储数据被分割成多个数据段，并且其中第二存储器部分被配置为存储将存储在第一存储器部分中的数据段的物理地址映射到数据段的逻辑地址的信息。

7. 发明授权

US09405618B2 Marker programming in non-volatile memories 有权
标题翻译：非易失性存储器中的标记编程
公开(公告)号：US09405618B2
公开(公告)日：2016-08-02
申请号：US14289311
申请日：2014-05-28
申请人： Infineon Technologies AG
发明人： Thomas Rabenalt , Ulrich Backhausen , Thomas Kern , Michael Goessel
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1012 , G11C16/10 , G11C16/26 , G11C29/52 , G11C2029/0411 , H03M13/13
摘要： A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
摘要翻译：公开了一种用于访问非易失性存储器的方法和存储器控制器。该方法包括读取非易失性存储器的第一存储器区域，确定第一存储器区域是否包含预定数据模式，其中预定数据模式对至少第一存储区域确定的所得到的纠错数据没有影响。该方法基于第一存储器区域中的预定数据模式的存在来评估非易失性存储器的第二存储器区域的数据状态，其中数据状态指示是否存在有效数据中的至少一个第二存储器区域以及第二存储器区域是否可写入。

8. 发明申请

US20150212877A1 APPARATUS AND METHOD FOR IMPROVING DATA STORAGE BY DATA INVERSION 有权
标题翻译：通过数据转换改进数据存储的装置和方法
公开(公告)号：US20150212877A1
公开(公告)日：2015-07-30
申请号：US14166360
申请日：2014-01-28
申请人： Infineon Technologies AG
发明人： Thomas Kern , Karl Hofmann , Michael Goessel
IPC分类号： G06F11/10 , G11C29/02 , G11C16/06 , G11C11/16 , G11C13/00
CPC分类号： G06F11/1008 , G06F11/1012 , G11C7/1006 , G11C11/165 , G11C11/1675 , G11C13/0021 , G11C13/0069 , G11C16/06 , G11C29/025 , G11C2029/0411 , H03M13/00 , H03M13/13 , H03M13/152 , H03M13/19 , H03M13/353 , H03M13/611 , H03M13/618
摘要： An apparatus includes a processing unit and a memory. The processing unit is configured to encode a plurality of bits to obtain a plurality of encoded bits, the processing unit is configured to determine an inversion decision. When the inversion decision indicates that the subset of the encoded bits shall not be inverted, the processing unit is configured to store, as a stored word, bits of the first codeword into the memory. When the inversion decision indicates that the subset of the encoded bits shall be inverted, the processing unit is configured to invert each encoded bit of a subset of the encoded bits to obtain a second codeword and to store the second codeword into the memory.
摘要翻译：一种装置包括处理单元和存储器。处理单元被配置为对多个比特进行编码以获得多个编码比特，所述处理单元被配置为确定反演决定。当反转决定指示编码比特的子集不被反转时，处理单元被配置为将第一码字的比特存储到存储器中作为存储字。当反转决定指示编码比特的子集应被反转时，处理单元被配置为反转编码比特的子集的每个编码比特以获得第二码字并将第二码字存储到存储器中。

9. 发明授权

US08935590B2 Circuitry and method for multi-bit correction 有权
标题翻译：多位校正的电路和方法
公开(公告)号：US08935590B2
公开(公告)日：2015-01-13
申请号：US13664495
申请日：2012-10-31
申请人： Infineon Technologies AG
发明人： Thomas Kern , Michael Goessel
IPC分类号： G11C29/00 , G06F11/10 , G11C7/10
CPC分类号： G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F11/1076 , G11C7/1006
摘要： A circuitry is provided that includes a memory including a plurality of memory cells, wherein at least one of the plurality of memory cells of the memory is configured to take on one of at least three different states. The circuitry also includes a first subcircuit BT configured to generate a plurality of ternary output values based on a sequence of binary values, a second subcircuit LH configured to transform one or more ternary state values into binary auxiliary read values based on the one or more state values, and an encoder configured to generate one or more binary check bits, wherein the encoder is configured to store each of the generated one or more check bits in a different memory cell.
摘要翻译：提供了一种电路，其包括包括多个存储器单元的存储器，其中存储器的多个存储器单元中的至少一个被配置为采取至少三种不同状态中的一种。电路还包括第一子电路BT，其被配置为基于二进制值的序列产生多个三进制输出值，第二子电路LH被配置为基于一个或多个状态将一个或多个三态状态值转换为二进制辅助读取值值和被配置为生成一个或多个二进制校验位的编码器，其中所述编码器被配置为将所生成的一个或多个校验位中的每一个存储在不同的存储器单元中。

10. 发明申请

US20140198583A1 Method and System for Reducing the Size of Nonvolatile Memories 审中-公开
标题翻译：减少非易失性存储器尺寸的方法和系统
公开(公告)号：US20140198583A1
公开(公告)日：2014-07-17
申请号：US13743409
申请日：2013-01-17
申请人： INFINEON TECHNOLOGIES AG
发明人： Thomas Kern , Jens Rosenbusch , Ulrich Backhausen , Thomas Nirschl
IPC分类号： G11C16/24 , G11C16/10 , G11C16/14
CPC分类号： G11C16/14 , G11C16/0433 , G11C16/0466 , G11C16/10 , G11C16/24 , G11C16/26
摘要： Embodiments relate to system and methods including a plurality of nonvolatile memory elements wherein sets of least two nonvolatile memory elements each share one select element for selecting one of the nonvolatile memory elements of a particular one of the sets of nonvolatile memory elements for a read operation or a program operation.
摘要翻译：实施例涉及包括多个非易失性存储器元件的系统和方法，其中至少两个非易失性存储器元件的集合共享一个选择元件，用于选择用于读取操作的非易失性存储器元件组中的特定一个的非易失性存储器元件之一，一个程序操作。

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