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1. 发明申请

US20170062240A1 METHOD FOR MANUFACTURING A WAFER LEVEL PACKAGE 审中-公开
标题翻译：制造水平包装的方法
公开(公告)号：US20170062240A1
公开(公告)日：2017-03-02
申请号：US14835687
申请日：2015-08-25
申请人： Inotera Memories, Inc.
发明人： Tieh-Chiang Wu , Shing-Yih Shih
IPC分类号： H01L21/48 , H01L23/00 , H01L21/768 , H01L23/498 , H01L21/56 , H01L21/02
CPC分类号： H01L21/4853 , H01L21/02164 , H01L21/0217 , H01L21/486 , H01L21/561 , H01L21/6836 , H01L21/76831 , H01L21/7684 , H01L23/147 , H01L23/295 , H01L23/3128 , H01L23/49816 , H01L23/5383 , H01L23/5384 , H01L23/562 , H01L24/16 , H01L24/81 , H01L24/97 , H01L25/0655 , H01L25/50 , H01L2221/68327 , H01L2224/16227 , H01L2224/81007 , H01L2224/81192 , H01L2224/97 , H01L2924/1432 , H01L2924/1434 , H01L2924/15311 , H01L2924/157 , H01L2924/18161 , H01L2924/3511 , H01L2224/81
摘要： A method for fabricating a wafer level package is disclosed. A substrate having a top surface and a bottom surface is provided. A first dielectric layer is formed on the top surface. A redistribution layer (RDL) is formed on the first dielectric layer. The RDL comprises at least a second dielectric layer and at least a metal layer in the second dielectric layer. A first passivation layer is formed on the RDL. Bumps are formed in the first passivation layer. A chip is mounted on the RDL. The chip is electrically connected to the metal layer through the bumps. A molding compound is applied on the first passivation layer and around the chip. The bottom surface of the substrate is grinded until a remaining thickness of the substrate is reached. A plurality of through substrate vias is formed in the substrate.
摘要翻译：公开了一种制造晶片级封装的方法。提供具有顶表面和底表面的基底。第一电介质层形成在顶表面上。在第一电介质层上形成再分布层（RDL）。 RDL包括至少第二电介质层和至少第二介电层中的金属层。在RDL上形成第一钝化层。在第一钝化层中形成凸起。芯片安装在RDL上。芯片通过凸块与金属层电连接。将模塑料施加在第一钝化层上和芯片周围。研磨基板的底面，直到达到基板的剩余厚度。在衬底中形成多个通过衬底通孔。

2. 发明授权

US09570369B1 Semiconductor package with sidewall-protected RDL interposer and fabrication method thereof 有权
标题翻译：具有侧壁保护的RDL插入件的半导体封装及其制造方法
公开(公告)号：US09570369B1
公开(公告)日：2017-02-14
申请号：US15068649
申请日：2016-03-14
申请人： INOTERA MEMORIES, INC.
发明人： Shing-Yih Shih , Tieh-Chiang Wu
IPC分类号： H01L21/00 , H01L23/31 , H01L25/065 , H01L25/00 , H01L23/498 , H01L21/56 , H01L21/78
CPC分类号： H01L21/481 , H01L21/4857 , H01L21/561 , H01L21/568 , H01L21/78 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/5383 , H01L24/97 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L2224/16225 , H01L2224/81005 , H01L2224/81192 , H01L2224/97 , H01L2924/1511 , H01L2924/15192 , H01L2924/15311 , H01L2924/1816 , H01L2924/18161 , H01L2924/182 , H01L2224/81
摘要： A semiconductor package includes a redistributed layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the RDL interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the RDL interposer; and a plurality of solder bumps or solder balls mounted on the second side.
摘要翻译：半导体封装包括具有第一侧，与第一侧相对的第二侧的再分布层（RDL）插入件和在第一侧和第二侧之间延伸的垂直侧壁; 安装在RDL插入件的第一侧上的至少一个半导体管芯; 设置在第一侧并覆盖RDL插入件的至少一个半导体管芯和垂直侧壁的模塑料; 以及安装在第二侧上的多个焊料凸块或焊球。

3. 发明申请

US20160336413A1 RECESS ARRAY DEVICE WITH REDUCED CONTACT RESISTANCE 审中-公开
标题翻译：具有降低接触电阻的接收阵列设备
公开(公告)号：US20160336413A1
公开(公告)日：2016-11-17
申请号：US14714334
申请日：2015-05-17
申请人： INOTERA MEMORIES, INC.
发明人： Tieh-Chiang Wu
IPC分类号： H01L29/423 , H01L23/535 , H01L27/108
CPC分类号： H01L29/4236 , H01L21/31155 , H01L27/10823 , H01L29/0847 , H01L29/78
摘要： A recess array device includes a semiconductor substrate having a main surface; a recessed trench in the main surface of the semiconductor substrate; a gate electrode disposed at a lower portion of the recessed trench; a liner layer disposed on directly on the gate electrode and being in direct contact with the gate electrode; a gate dielectric layer disposed only between the gate electrode and the semiconductor substrate and between the liner layer and the semiconductor substrate; and an epitaxial silicon layer disposed at an upper portion of the recessed trench.
摘要翻译：凹部阵列器件包括具有主表面的半导体衬底; 在半导体衬底的主表面中的凹槽; 设置在所述凹槽的下部的栅电极; 直接设置在栅电极上并与栅电极直接接触的衬垫层; 仅在所述栅电极和所述半导体衬底之间以及所述衬垫层和所述半导体衬底之间设置的栅介质层; 以及设置在凹槽的上部的外延硅层。

4. 发明授权

US09449935B1 Wafer level package and fabrication method thereof 有权
标题翻译：晶圆级封装及其制造方法
公开(公告)号：US09449935B1
公开(公告)日：2016-09-20
申请号：US14810415
申请日：2015-07-27
申请人： INOTERA MEMORIES, INC.
发明人： Shing-Yih Shih , Tieh-Chiang Wu
IPC分类号： H01L23/544 , H01L23/00 , H01L23/31 , H01L23/528 , H01L23/532 , H01L23/522
CPC分类号： H01L24/97 , H01L21/4857 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/145 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L2221/68345 , H01L2224/13023 , H01L2224/13147 , H01L2224/16113 , H01L2224/16227 , H01L2224/16235 , H01L2224/81005 , H01L2224/97 , H01L2924/15311 , H01L2924/3511 , H01L2924/381 , H01L2224/81 , H01L2924/00014
摘要： A semiconductor device includes a chip having an active surface and a rear surface that is opposite to the active surface; a molding compound covering and encapsulating the chip except for the active surface; and a redistribution layer (RDL) on the active surface and on the molding compound. The RDL is electrically connected to the chip. The RDL includes an organic dielectric layer and an inorganic dielectric hard mask layer on the organic dielectric layer. The RDL further includes metal features in the organic dielectric layer and the inorganic dielectric hard mask layer.
摘要翻译：半导体器件包括具有活性表面和与活性表面相对的后表面的芯片; 覆盖并封装除了活性表面之外的芯片的模塑料; 以及在活性表面和模塑料上的再分布层（RDL）。 RDL电连接到芯片。 RDL在有机介电层上包括有机电介质层和无机介电硬掩模层。 RDL还包括有机介电层和无机电介质硬掩模层中的金属特征。

5. 发明授权

US09397048B1 Semiconductor structure and manufacturing method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09397048B1
公开(公告)日：2016-07-19
申请号：US14664932
申请日：2015-03-23
申请人： Inotera Memories, Inc.
发明人： Shing-Yih Shih , Tieh-Chiang Wu
IPC分类号： H01L23/48 , H01L23/535 , H01L21/768
CPC分类号： H01L21/76877 , H01L21/76224 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a substrate, a first through hole disposed in the substrate and filled with conductive material, and a second through hole disposed in the substrate and filled with isolation material, which a Young's modulus of the isolation material is smaller than a Young's modulus of the conductive material to balance stress from the conductive material.
摘要翻译：半导体结构包括基板，设置在基板中并填充有导电材料的第一通孔和设置在基板中并填充隔离材料的第二通孔，隔离材料的杨氏模量小于杨氏模量的导电材料以平衡来自导电材料的应力。

6. 发明授权

US09419001B1 Method for forming cell contact 有权
标题翻译：细胞接触形成方法
公开(公告)号：US09419001B1
公开(公告)日：2016-08-16
申请号：US14996240
申请日：2016-01-15
申请人： INOTERA MEMORIES, INC.
发明人： Sheng-Wei Yang , Tieh-Chiang Wu , Wen-Chieh Wang
IPC分类号： H01L21/76 , H01L27/108
CPC分类号： H01L27/10888 , H01L27/108 , H01L27/10814 , H01L27/10844 , H01L27/10855 , H01L27/10876
摘要： A method for forming a cell contact. A substrate having first and second protruding structures is prepared. An etch stop layer is deposited over the substrate. A sacrificial layer is deposited on the etch stop layer. The sacrificial layer is recessed. Spacers are formed on the top surface of the sacrificial layer. A portion of the sacrificial layer not covered by the spacers is etched away, thereby forming a recess. A gap filling material layer is deposited into the recess. An upper portion of the gap filling material layer and the spacers are removed to expose the top surface of the sacrificial layer. The sacrificial layer is removed to form contact holes. A punch etching process is performed to remove the etch stop layer from bottoms of the contact holes. The contact holes is filled up with a conductive material layer.
摘要翻译：一种形成细胞接触的方法。准备具有第一和第二突出结构的基板。蚀刻停止层沉积在衬底上。牺牲层沉积在蚀刻停止层上。牺牲层凹进。间隔物形成在牺牲层的顶表面上。不被间隔物覆盖的牺牲层的一部分被蚀刻掉，从而形成凹陷。间隙填充材料层沉积到凹槽中。去除间隙填充材料层和间隔物的上部以暴露牺牲层的顶表面。去除牺牲层以形成接触孔。执行冲孔蚀刻工艺以从接触孔的底部去除蚀刻停止层。接触孔填充有导电材料层。

7. 发明授权

US09472664B1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09472664B1
公开(公告)日：2016-10-18
申请号：US14803100
申请日：2015-07-19
申请人： Inotera Memories, Inc.
发明人： Tieh-Chiang Wu
IPC分类号： H01L29/15 , H01L31/0312 , H01L29/78 , H01L29/423 , H01L29/16 , H01L29/161 , H01L29/66 , H01L27/108
CPC分类号： H01L29/7827 , H01L27/10876 , H01L29/1054 , H01L29/1608 , H01L29/161 , H01L29/4236 , H01L29/66666 , H01L29/78
摘要： The present disclosure provides a semiconductor device including a substrate, a gate structure, a channel layer, a first active region and a second active region. The gate structure is disposed in the substrate. The channel layer is sandwiched between the gate structure and the substrate. A material of the channel layer is selected from the group consisting of silicon-germanium epitaxial material, silicon-carbon epitaxial material, and a combination thereof. The first active region and the second active region are disposed in the substrate and respectively disposed at opposite sides of the gate structure. A method for manufacturing a semiconductor device is provided herein.
摘要翻译：本公开提供了一种包括衬底，栅极结构，沟道层，第一有源区和第二有源区的半导体器件。栅极结构设置在基板中。沟道层夹在栅极结构和衬底之间。沟道层的材料选自硅 - 锗外延材料，硅 - 碳外延材料及其组合。第一有源区和第二有源区设置在衬底中并且分别设置在栅极结构的相对侧。本发明提供半导体器件的制造方法。

8. 发明授权

US09379197B1 Recess array device 有权
标题翻译：凹槽阵列装置
公开(公告)号：US09379197B1
公开(公告)日：2016-06-28
申请号：US14877889
申请日：2015-10-07
申请人： INOTERA MEMORIES, INC.
发明人： Tieh-Chiang Wu , Shing-Yih Shih
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423 , H01L29/78 , H01L27/108
CPC分类号： H01L29/42368 , H01L21/26506 , H01L27/10823 , H01L27/10876 , H01L29/0649 , H01L29/4236 , H01L29/78
摘要： A recess array device includes a semiconductor substrate and at least an active area in a main surface of the semiconductor substrate. A gate trench penetrates through the active area. The gate trench includes a first sidewall, a second sidewall facing the first sidewall, and a bottom surface extending between the first and the second sidewalls. A bump portion is disposed in the gate trench. The bump portion has two opposite sidewalls and a top portion extending between the two opposite sidewalls. A gate oxide layer is formed in the gate trench. The gate oxide layer has a first thickness on the first and second sidewalls, a second thickness on the two opposite sidewalls of the bump portion, and a third thickness on the top portion of the bump portion. The first thickness is greater than the second thickness. The second thickness is greater than the third thickness.
摘要翻译：凹部阵列器件包括半导体衬底和半导体衬底的主表面中的至少一个有源区域。栅极沟槽穿过有源区域。栅极沟槽包括第一侧壁，面向第一侧壁的第二侧壁和在第一和第二侧壁之间延伸的底表面。突起部分设置在栅极沟槽中。凸起部分具有两个相对的侧壁和在两个相对侧壁之间延伸的顶部部分。栅极氧化层形成在栅极沟槽中。栅极氧化物层在第一和第二侧壁上具有第一厚度，在凸起部分的两个相对的侧壁上具有第二厚度，并且在凸起部分的顶部上具有第三厚度。第一厚度大于第二厚度。第二厚度大于第三厚度。

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