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1. 发明授权

US09412657B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09412657B2
公开(公告)日：2016-08-09
申请号：US14943706
申请日：2015-11-17
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Chao Zhao , Huilong Zhu
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/49827
摘要： In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.
摘要翻译：在制造半导体的方法中，透明硅（TSV）模板晶片和生产晶片形成夹层结构，其中TSV模板晶片具有均匀分布在其中的TSV结构，用于在生产晶片之间提供电连接以形成3D互连。通过减薄半导体晶片获得TSV模板晶片，这有助于降低蚀刻和填充的难度。在TSV模板晶片上提供连接部件，以方便上层和下面的生产晶圆之间的互连，这有助于降低对准难度，并提高3D设备电气连接设计的便利性。

2. 发明授权

US09331182B2 Semiconductor devices with a gate conductor formed as a spacer, and methods for manufacturing the same 有权
标题翻译：具有形成为间隔物的栅极导体的半导体器件及其制造方法
公开(公告)号：US09331182B2
公开(公告)日：2016-05-03
申请号：US14151441
申请日：2014-01-09
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/788 , H01L29/66 , H01L21/28 , H01L29/423
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7881
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one aspect, the method comprises forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask. Then, forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. Then, removing a portion of the second shielding layer which is next to the other of the source and drain regions. Lastly, forming a first gate dielectric layer, a floating gate layer, and a second gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.
摘要翻译：公开了半导体装置及其制造方法。一方面，该方法包括在衬底上形成第一屏蔽层，并且将第一屏蔽层作为掩模形成源区和漏区之一。然后，在衬底上形成第二屏蔽层，并且用第二屏蔽层作为掩模形成源区和漏区中的另一个。然后，去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。最后，形成第一栅极电介质层，浮栅层和第二栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

3. 发明申请

US20150054074A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150054074A1
公开(公告)日：2015-02-26
申请号：US14389095
申请日：2012-10-08
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/28079 , H01L21/28141 , H01L21/2815 , H01L21/823842 , H01L27/11568 , H01L29/105 , H01L29/4983 , H01L29/66545 , H01L29/66598 , H01L29/66636 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7833 , H01L29/7843 , H01L2029/42388
摘要： Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.
摘要翻译：提供半导体器件及其制造方法。在一个实施例中，该方法可以包括：在衬底上形成第一屏蔽层; 以所述第一屏蔽层为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并移除所述第一屏蔽层; 在所述第二屏蔽层的侧壁上形成屏蔽间隔物; 用第二屏蔽层和屏蔽间隔物作为掩模形成源极和漏极区域中的另一个; 去除所述屏蔽间隔物的至少一部分; 以及形成栅极电介质层，并且在所述第二屏蔽层的侧壁或所述屏蔽间隔物的可能的剩余部分上形成作为间隔物的栅极导体。

4. 发明授权

US11251183B2 Semiconductor arrangement having continuous spacers and method of manufacturing the same 有权
公开(公告)号：US11251183B2
公开(公告)日：2022-02-15
申请号：US17039755
申请日：2020-09-30
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Yanbo Zhang , Huicai Zhong
IPC分类号： H01L27/092 , H01L29/66 , H01L21/8234 , H01L29/78
摘要： A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

5. 发明授权

US09806169B2 Semiconductor devices having a gate stack 有权
公开(公告)号：US09806169B2
公开(公告)日：2017-10-31
申请号：US14389055
申请日：2012-11-26
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L29/49 , H01L21/265
CPC分类号： H01L29/6656 , H01L21/2658 , H01L21/26586 , H01L29/105 , H01L29/1083 , H01L29/4983 , H01L29/6653 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7833 , H01L29/7835 , H01L29/7843
摘要： Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate.

6. 发明授权

US09379056B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09379056B2
公开(公告)日：2016-06-28
申请号：US14423020
申请日：2012-09-17
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/311 , H01L21/3213 , H01L23/528 , H01L21/768 , H01L23/532
CPC分类号： H01L23/528 , H01L21/31111 , H01L21/32133 , H01L21/76802 , H01L21/76831 , H01L21/76838 , H01L21/76841 , H01L21/76877 , H01L21/76892 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners.
摘要翻译：本发明提供一种制造半导体结构的方法，包括：a）在衬底上形成金属互连衬垫; b）形成掩模层以覆盖金属互连衬里并在掩模层上形成露出金属互连衬套的开口; c）经由开口蚀刻和断开金属互连衬套，由此绝缘和隔离金属互连衬套。本发明还提供一种半导体结构，其包括衬底和金属互连衬套，其中金属互连衬里的端部通过在衬底内形成的绝缘壁而断开。本发明提供的结构和方法有利于缩短相邻金属互连衬套的端部之间的距离，节省器件面积并抑制金属互连衬套发生的短路。

7. 发明授权

US09306016B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09306016B2
公开(公告)日：2016-04-05
申请号：US14423395
申请日：2012-09-17
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L21/00 , H01L29/00 , H01L29/417 , H01L29/66 , H01L29/786 , H01L21/02 , H01L21/306 , H01L21/311 , H01L21/762 , H01L29/06 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/78 , H01L29/165
CPC分类号： H01L29/41783 , H01L21/02181 , H01L21/02192 , H01L21/02194 , H01L21/30604 , H01L21/31111 , H01L21/31116 , H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/66772 , H01L29/66825 , H01L29/7848 , H01L29/78654
摘要： The present invention provides a method for manufacturing a semiconductor device, which comprises: providing an SOI substrate, which comprises a base layer, an insulating layer located on the base layer and a active layer located on the insulating layer; forming a gate stack on the SOI substrate; etching the active layer, the insulating layer and a part of the base layer of the SOI substrate with the gate stack as a mask, so as to form trenches on both sides of the gate stack; forming a crystal dielectric layer within the trenches, wherein the upper surface of the crystal dielectric layer is lower than the upper surface of the insulating layer and not lower than the lower surface of the insulating layer; and forming source/drain regions on the crystal dielectric layer. The present invention further provides a semiconductor device. The present invention is capable of eliminating pathway for leakage current between source/drain regions and SOI substrate at the meantime of reducing contact resistance at source/drain regions.
摘要翻译：本发明提供一种制造半导体器件的方法，其包括：提供SOI衬底，其包括基底层，位于基底层上的绝缘层和位于绝缘层上的有源层; 在SOI衬底上形成栅叠层; 用栅极叠层作为掩模蚀刻有源层，绝缘层和SOI衬底的基底层的一部分，以在栅叠层的两侧形成沟槽; 在所述沟槽内形成晶体介质层，其中所述晶体介质层的上表面低于所述绝缘层的上表面，并且不低于所述绝缘层的下表面; 并在晶体介质层上形成源/漏区。本发明还提供一种半导体器件。本发明能够消除源极/漏极区域和SOI衬底之间的泄漏电流的途径，同时降低源极/漏极区域的接触电阻。

8. 发明授权

US10832972B2 Semiconductor arrangement having continuous spacers and method of manufacturing the same 有权
公开(公告)号：US10832972B2
公开(公告)日：2020-11-10
申请号：US16327973
申请日：2016-12-21
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Huicai Zhong , Yanbo Zhang
IPC分类号： H01L21/8238 , H01L29/66 , H01L27/092 , H01L21/8234 , H01L29/78 , H01L29/165
摘要： A semiconductor arrangement includes: a substrate; a plurality of fins formed on the substrate and extending in a first direction; a plurality of gate stacks formed on the substrate and extending in a second direction crossing the first direction and dummy gates composed of dielectric and extending in the second direction, wherein each of the gate stacks intersects at least one of the fins; and spacers formed on sidewalls of the gate stacks and sidewalls of the dummy gates, wherein spacers of at least a first one and a second one among the gate stacks and the dummy gates which are aligned in the second direction extend integrally, and at least some of the fins have ends abutting the dummy gates and substantially aligned with inner walls of corresponding ones of the spacers.

9. 发明授权

US10269919B2 Semiconductor device structure and method for fabricating the same 有权
公开(公告)号：US10269919B2
公开(公告)日：2019-04-23
申请号：US15630356
申请日：2017-06-22
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L27/02 , H01L29/49 , H01L21/768 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L27/105 , H01L27/088 , H01L27/108
摘要： A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the first and second devices includes a gate extending in a first direction, source/drain regions respectively formed on opposite first and second sides of the gate, dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side, and conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers. A second direction from the source/drain region on the first side to the source/drain region on the second side crosses the first direction.

10. 发明授权

US09397007B2 Method for manufacturing semiconductor structure through forming an additional layer inside opening of a photoresist layer 有权
标题翻译：通过在光致抗蚀剂层的开口内形成附加层来制造半导体结构的方法
公开(公告)号：US09397007B2
公开(公告)日：2016-07-19
申请号：US14652956
申请日：2013-07-26
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huicai Zhong , Qingqing Liang , Da Yang , Chao Zhao
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/06 , H01L21/265 , H01L21/28 , H01L29/423 , H01L29/78
CPC分类号： H01L21/823437 , H01L21/26533 , H01L21/28176 , H01L21/823468 , H01L27/088 , H01L29/0653 , H01L29/4238 , H01L29/78
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending in a direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings across the gate lines; c) narrowing the openings by forming a self-assembly copolymer inside the openings; and d) cutting the gate lines via the openings to make the gate lines insulated at the openings. Through forming an additional layer on the inner wall of the openings of the photoresist layer, the method for manufacturing a semiconductor structure provided by the present invention manages to reduce the distance between the two opposite walls of the openings in the direction of gate width, namely, the method manages to reduce the distance between the ends of electrically isolated gates located on the same line where it is unnecessary to manufacture a cut mask whose lines are extremely fine. Working area is therefore saved, which accordingly improves integration level of semiconductor devices. In addition, the present invention further provides a semiconductor structure according to the method provided by the present invention.
摘要翻译：本发明提供一种制造半导体结构的方法，其包括：a）形成沿衬底方向延伸的栅极线; b）形成覆盖半导体结构的光致抗蚀剂层; 图案化光致抗蚀剂层以在栅极线上形成开口; c）通过在开口内形成自组装共聚物来缩小开口; 以及d）经由所述开口切割所述栅极线以使所述栅极线在所述开口处绝缘。通过在光致抗蚀剂层的开口的内壁上形成附加层，本发明提供的半导体结构的制造方法旨在减小开口方向的两个相对壁之间在栅极宽度方向上的距离，即该方法旨在减少位于同一线路上的电隔离门的端部之间的距离，其中不需要制造线极细的切割掩模。因此节省了工作区域，从而提高了半导体器件的集成度。此外，本发明还提供根据本发明提供的方法的半导体结构。

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