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1. 发明申请

US20230039853A1 WORKLOAD SCHEDULING AND DISTRIBUTION ON A DISTRIBUTED GRAPHICS DEVICE 有权
公开(公告)号：US20230039853A1
公开(公告)日：2023-02-09
申请号：US17968469
申请日：2022-10-18
申请人： Intel Corporation
发明人： Balaji Vembu , Brandon Fliflet , James Valerio , Michael Apodaca , Ben Ashbaugh , Hema Nalluri , Ankur Shah , Murali Ramadoss , David Puffer , Altug Koker , Aditya Navale , Abhishek R. Appu , Joydeep Ray , Travis Schluessler
IPC分类号： G06T1/20 , G06F9/48 , G06F9/50 , G06F9/52 , G06T1/60
摘要： Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

2. 发明授权

US11481864B2 Workload scheduling and distribution on a distributed graphics device 有权
公开(公告)号：US11481864B2
公开(公告)日：2022-10-25
申请号：US17234039
申请日：2021-04-19
申请人： Intel Corporation
发明人： Balaji Vembu , Brandon Fliflet , James Valerio , Michael Apodaca , Ben Ashbaugh , Hema Nalluri , Ankur Shah , Murali Ramadoss , David Puffer , Altug Koker , Aditya Navale , Abhishek R. Appu , Joydeep Ray , Travis Schluessler
IPC分类号： G06T1/20 , G06F9/48 , G06F9/50 , G06F9/52 , G06T1/60
摘要： Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

3. 发明申请

US20220262070A1 TILE SEQUENCING MECHANISM 有权
公开(公告)号：US20220262070A1
公开(公告)日：2022-08-18
申请号：US17590521
申请日：2022-02-01
申请人： Intel Corporation
发明人： Subramaniam Maiyuran , Saurabh Sharma , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Justin Decell , Aditya Navale
IPC分类号： G06T17/20 , G06T1/20 , G06T15/00
摘要： An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.

4. 发明申请

US20210349717A1 COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS 有权
公开(公告)号：US20210349717A1
公开(公告)日：2021-11-11
申请号：US16914030
申请日：2020-06-26
申请人： Intel Corporation
发明人： Chandra Gurram , Subramaniam Maiyuran , Supratim Pal , Saurabh Sharma , Aditya Navale
IPC分类号： G06F9/30 , G06F9/38 , G06F7/57 , G06F1/14
摘要： Described herein is an accelerator device in which compaction of diverged lanes of a parallel processor is enabled to increase the efficiency of ALU utilization. One embodiment provides an accelerator device comprising a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including a parallel processing architecture configured to enable compaction of diverged lanes.

5. 发明申请

US20200341766A1 MEMORY MAPPED VIRTUAL DOORBELL MECHANISM 审中-公开
公开(公告)号：US20200341766A1
公开(公告)日：2020-10-29
申请号：US16397217
申请日：2019-04-29
申请人： Intel Corporation
发明人： Bryan R. White , Ankur N. Shah , Altug Koker , David Puffer , Aditya Navale
IPC分类号： G06F9/30 , G06F12/0831 , G06F12/0837 , G06F9/48 , G06F9/54 , G06F9/38
摘要： An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.

6. 发明授权

US09886934B2 Ordering mechanism for offload graphics scheduling 有权
公开(公告)号：US09886934B2
公开(公告)日：2018-02-06
申请号：US14582972
申请日：2014-12-24
申请人： Intel Corporation
发明人： Bryan R. White , Balaji Vembu , Murali Ramadoss , Altug Koker , Aditya Navale
IPC分类号： G09G5/18 , G06T1/20 , G09G5/02 , G09G5/14 , G09G5/36
CPC分类号： G09G5/18 , G06T1/20 , G09G5/026 , G09G5/14 , G09G5/363 , G09G2320/106 , G09G2340/02 , G09G2360/121 , G09G2360/18 , G09G2370/16
摘要： Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.

7. 发明授权

US09436972B2 System coherency in a distributed graphics processor hierarchy 有权
标题翻译：分布式图形处理器层次结构中的系统一致性
公开(公告)号：US09436972B2
公开(公告)日：2016-09-06
申请号：US14227525
申请日：2014-03-27
申请人： Intel Corporation
发明人： Altug Koker , Aditya Navale
IPC分类号： G09G5/36 , G06T1/00 , G06F15/00 , G06T1/60 , G06F12/08
CPC分类号： G06T1/60 , G06F12/0811 , G06F12/0813 , G06F12/0831 , G06F2212/1024 , G06F2212/455
摘要： Methods and systems may provide for executing, by a physically distributed set of compute slices, a plurality of work items. Additionally, the coherency of one or more memory lines associated with the plurality of work items may be maintained, by a cache fabric, across a graphics processor, a system memory and one or more host processors. In one example, a plurality of crossbar nodes track the one or more memory lines, wherein the coherency of the one or more memory lines is maintained across a plurality of level one (L1) caches and a physically distributed cache structure. Each L1 cache may be dedicated to an execution block of a compute slice and each crossbar node may be dedicated to a compute slice.
摘要翻译：方法和系统可以提供通过物理分布的计算片段来执行多个工作项目。此外，与多个工作项相关联的一个或多个存储器线的一致性可以由缓存结构跨图形处理器，系统存储器和一个或多个主机处理器来维护。在一个示例中，多个交叉开关节点跟踪一个或多个存储器线，其中一个或多个存储器线的一致性被保持在多个一级（L1）高速缓存和物理分布的高速缓存结构上。每个L1高速缓存可以专用于计算片的执行块，并且每个交叉节点可以专用于计算片。

8. 发明授权

US09323684B2 Dynamic cache and memory allocation for memory subsystems 有权
标题翻译：内存子系统的动态缓存和内存分配
公开(公告)号：US09323684B2
公开(公告)日：2016-04-26
申请号：US14221491
申请日：2014-03-21
申请人： Intel Corporation
发明人： Altug Koker , Aditya Navale
IPC分类号： G09G5/36 , G06T1/60 , G06F12/08
CPC分类号： G06F12/0871 , G06F12/0875 , G09G2360/121 , Y02D10/13
摘要： Technologies are presented that allow a portion of a cache to be used as a front memory when there is dynamic need based on system demand. A computing system may include at least one processor, a memory controlled by a controller and communicatively coupled with the at least one processor, a cache communicatively coupled with the at least one processor and the memory, and mapping logic communicatively coupled with the at least one processor, the memory, and the cache. The mapping logic may map a portion of the cache to a portion of the memory, wherein the portion of the cache is to be used by the at least one processor as a local memory, and wherein the mapping is dynamic based on system demand and managed by the controller in a physical address domain.
摘要翻译：当存在基于系统需求的动态需求时，提供允许一部分高速缓存用作前端存储器的技术。计算系统可以包括至少一个处理器，由控制器控制并与所述至少一个处理器通信耦合的存储器，与所述至少一个处理器和所述存储器通信地耦合的高速缓存器，以及与所述至少一个处理器通信耦合的映射逻辑处理器，内存和缓存。所述映射逻辑可将所述高速缓存的一部分映射到所述存储器的一部分，其中所述高速缓存的所述部分将由所述至少一个处理器用作本地存储器，并且其中所述映射基于系统需求而动态地被管理由控制器在物理地址域中。

9. 发明申请

US20220138286A1 GRAPHICS SECURITY WITH SYNERGISTIC ENCRYPTION, CONTENT-BASED AND RESOURCE MANAGEMENT TECHNOLOGY 有权
公开(公告)号：US20220138286A1
公开(公告)日：2022-05-05
申请号：US17133336
申请日：2020-12-23
申请人： Intel Corporation
发明人： David Zage , Scott Janus , Ned M. Smith , Vidhya Krishnan , Siddhartha Chhabra , Rajesh Poornachandran , Tomer Levy , Julien Carreno , Ankur Shah , Ronald Silvas , Aravindh Anantaraman , David Puffer , Vedvyas Shanbhogue , David Cowperthwaite , Aditya Navale , Omer Ben-Shalom , Alex Nayshtut , Xiaoyu Ruan
IPC分类号： G06F21/10 , G06F21/60 , G06T1/20 , G06F9/455
摘要： Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.

10. 发明授权

US11321262B2 Interconnected systems fence mechanism 有权
公开(公告)号：US11321262B2
公开(公告)日：2022-05-03
申请号：US17014023
申请日：2020-09-08
申请人： Intel Corporation
发明人： Hema Chand Nalluri , Ankur Shah , Joydeep Ray , Aditya Navale , Altug Koker , Murali Ramadoss , Niranjan L. Cooray , Jeffery S. Boles , Aravindh Anantaraman , David Puffer , James Valerio , Vasanth Ranganathan
IPC分类号： G06F9/52 , G06F12/14 , G06F13/40 , G06F13/16 , G06F12/0888 , G06F12/0837 , G06F9/30
摘要： An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.

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