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1. 发明授权

US11169929B2 Pause communication from I/O devices supporting page faults 有权
公开(公告)号：US11169929B2
公开(公告)日：2021-11-09
申请号：US15958591
申请日：2018-04-20
申请人： Intel Corporation
发明人： Rupin Vakharwala , Amin Firoozshahian , Stephen Van Doren , Rajesh Sankaran , Mahesh Madhav , Omid Azizi , Andreas Kleen , Mahesh Maddury , Ashok Raj
IPC分类号： G06F12/1009 , G06F3/06 , G06F12/0862 , G06F9/38 , G06F12/1081 , G06F12/1045 , G06F12/1027
摘要： A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.

2. 发明申请

US20210248026A1 DEVICE, SYSTEM AND METHOD TO IDENTIFY A SOURCE OF DATA POISONING 有权
公开(公告)号：US20210248026A1
公开(公告)日：2021-08-12
申请号：US17153337
申请日：2021-01-20
申请人： Intel Corporation
发明人： Mohan J. Kumar , Theodros Yigzaw , Murugasamy Nachimuthu , Ashok Raj , Jose Vargas
IPC分类号： G06F11/07
摘要： Techniques and mechanisms for a processor to efficiently identify a circuit resource as being a source of data poisoning. In an embodiment, metadata is communicated, in association with a communication of poisoned data to which the metadata pertains, to a first circuit block of a processor. The metadata indicates a poisoned state of the data, wherein the metadata identifies a second circuit block—which is included in or coupled to the processor—as being a poisoner of the data. Based on the metadata, the first circuit block generates a fault message which identifies the second circuit block as the poisoner of the data. In another embodiment, the processor further comprises the second circuit block, which poisons the data (based on the detection of an error condition) by providing in the metadata a unique identifier which is assigned to the second circuit block.

3. 发明授权

US11048512B1 Apparatus and method to identify the source of an interrupt 有权
公开(公告)号：US11048512B1
公开(公告)日：2021-06-29
申请号：US16833598
申请日：2020-03-28
申请人： Intel Corporation
发明人： Ashok Raj , Andreas Kleen , Gilbert Neiger , Beeman Strong , Jason Brandt , Rupin Vakharwala , Jeff Huxel , Larisa Novakovsky , Ido Ouziel , Sarathy Jayakumar
IPC分类号： G06F9/50 , G06F9/30 , G06F15/80 , G06F9/48
摘要： An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

4. 发明授权

US10430267B2 Determine when an error log was created 有权
公开(公告)号：US10430267B2
公开(公告)日：2019-10-01
申请号：US15206853
申请日：2016-07-11
申请人： INTEL CORPORATION
发明人： Ashok Raj , Narayan Ranganathan
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14
摘要： A computing system can include a machine check counter (MCC) including a current value. The current value indicates a system reboot resetting hardware of the computing system. The machine check counter includes a model specific register including a counter indicating the current value, the current value to be incremented upon the system reboot.

5. 发明申请

US20190213153A1 Management of Processor Performance Based on User Interrupts 审中-公开
公开(公告)号：US20190213153A1
公开(公告)日：2019-07-11
申请号：US15864290
申请日：2018-01-08
申请人： Intel Corporation
发明人： Jacob Jun Pan , Ashok Raj , Srinivas Pandruvada
IPC分类号： G06F13/24
摘要： In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

6. 发明授权

US10185619B2 Handling of error prone cache line slots of memory side cache of multi-level system memory 有权
公开(公告)号：US10185619B2
公开(公告)日：2019-01-22
申请号：US15087797
申请日：2016-03-31
申请人： INTEL CORPORATION
发明人： Theodros Yigzaw , Ashok Raj , Robert Swanson , Mohan J. Kumar
IPC分类号： G06F11/07 , G06F12/0804
摘要： An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.

7. 发明申请

US20160092220A1 Instruction and Logic for Machine Check Interrupt Management 有权
标题翻译：机器检查中断管理指令和逻辑
公开(公告)号：US20160092220A1
公开(公告)日：2016-03-31
申请号：US14498092
申请日：2014-09-26
申请人： Intel Corporation
发明人： Ashok Raj , Mohan J. Kumar
IPC分类号： G06F9/30
CPC分类号： G06F9/30072 , G06F9/30076 , G06F9/30109 , G06F9/3861
摘要： A processor includes a front end including a decoder to decode an instruction, a scheduler to assign execution of the instruction to a core, and a core to execute the instruction. The instruction specifies that interrupts such as corrected machine check interrupts are to be selectively suppressed. The processor further includes an error handling unit including logic to determine that an interrupt caused by an error is to be created and that an error consumer has requested interrupt notification. The error handling unit further includes logic to, based on the instruction specifying that interrupts are to be selectively suppressed, send the interrupt to a producer that issued the instruction rather than the error consumer.
摘要翻译：处理器包括前端，其包括用于解码指令的解码器，向核心分配指令执行的调度器以及执行指令的核心。该指令指定要选择性地抑制诸如校正机器检查中断之类的中断。该处理器还包括错误处理单元，其包括用于确定由错误引起的中断将被创建并且错误消费者已经请求中断通知的逻辑。错误处理单元还包括基于指定要被选择性地抑制中断的指令的逻辑，将中断发送给发出指令而不是错误消费者的生产者。

8. 发明授权

US11307996B2 Hardware unit for reverse translation in a processor 有权
公开(公告)号：US11307996B2
公开(公告)日：2022-04-19
申请号：US16206516
申请日：2018-11-30
申请人： Intel Corporation
发明人： Sarathy Jayakumar , Ashok Raj , Wei P. Chen , Theodros Yigzaw , John Holm
IPC分类号： G06F12/1027 , G06F12/0864 , G06F13/16 , G06F11/22 , G06F9/38
摘要： In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.

9. 发明授权

US11269782B2 Address space identifier management in complex input/output virtualization environments 有权
公开(公告)号：US11269782B2
公开(公告)日：2022-03-08
申请号：US16772765
申请日：2018-03-28
申请人： INTEL CORPORATION
发明人： Kun Tian , Xiao Zheng , Ashok Raj , Sanjay Kumar , Rajesh Sankaran
IPC分类号： G06F12/1036 , G06F9/455 , G06F12/1081
摘要： Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.

10. 发明授权

US10324852B2 System and method to increase availability in a multi-level memory configuration 有权
公开(公告)号：US10324852B2
公开(公告)日：2019-06-18
申请号：US15374796
申请日：2016-12-09
申请人： INTEL CORPORATION
发明人： Theodros Yigzaw , Ashok Raj , Robert C. Swanson , Mohan J. Kumar
IPC分类号： G06F11/00 , G06F12/0868 , G06F11/20 , G06F12/109
摘要： One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.

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