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1. 发明申请

US20220222203A1 ENABLING STATELESS ACCELERATOR DESIGNS SHARED ACROSS MUTUALLY-DISTRUSTFUL TENANTS 有权
公开(公告)号：US20220222203A1
公开(公告)日：2022-07-14
申请号：US17712350
申请日：2022-04-04
申请人： Intel Corporation
发明人： Alpa Trivedi , Carlos Rozas
IPC分类号： G06F15/78 , G06F30/398 , G06N3/04 , H04L9/08 , G06F9/30 , G06F9/50 , G06F15/177 , H04L9/40 , G06F11/07 , G06F30/331 , G06F9/38
摘要： An apparatus to facilitate enabling stateless accelerator designs shared across mutually-distrustful tenants is disclosed. The apparatus includes a fully-homomorphic encryption (FHE)-capable circuitry to establish a secure session with a trusted environment executing on a host device communicably coupled to the apparatus; generate, as part of establishing the secure session, per-tenant FHE keys for each tenant utilizing the FHE-capable circuitry, the per-tenant FHE keys utilized to encrypt tenant data provided to an FHE-capable compute kernel of the FHE-capable circuitry; process tenant data that is in an FHE-encrypted format encrypted with a per-tenant FHE key of the per-tenant FHE keys; and store the tenant data that is in the FHE-encrypted format encrypted with the per-tenant FHE key of the per-tenant FHE keys.

2. 发明授权

US09729309B2 Securing data transmission between processor packages 有权
公开(公告)号：US09729309B2
公开(公告)日：2017-08-08
申请号：US13719939
申请日：2012-12-19
申请人： Intel Corporation
发明人： Simon Johnson , Abhishek Das , Carlos Rozas , Uday Savagaonkar , Robert Blankenship , Kiran Padwekar
IPC分类号： G06F21/00 , H04L29/06 , H04L9/32 , H04L9/00
CPC分类号： H04L9/00 , G06F21/556 , G06F21/606 , H04L9/32 , H04L63/0428 , H04L63/0471 , H04L63/123
摘要： Embodiments of an invention for securing transmissions between processor packages are disclosed. In one embodiment, an apparatus includes an encryption unit to encrypt first content to be transmitted from the apparatus to a processor package directly through a point-to-point link.

3. 发明授权

US09407636B2 Method and apparatus for securely saving and restoring the state of a computing platform 有权
标题翻译：安全地保存和恢复计算平台状态的方法和装置
公开(公告)号：US09407636B2
公开(公告)日：2016-08-02
申请号：US14281651
申请日：2014-05-19
申请人： INTEL CORPORATION
发明人： Vincent Scarlata , Simon Johnson , Carlos Rozas , Francis McKeen , Ittai Anati , Ilya Alexandrovich , Rebekah Leslie-Hurd
IPC分类号： G06F21/64 , H04L29/06 , G06F21/74
CPC分类号： G06F21/64 , G06F21/62 , G06F21/74 , G06F21/81 , G06F21/85 , H04L63/061 , H04L63/0876
摘要： An apparatus and method for securely suspending and resuming the state of a processor. For example, one embodiment of a method comprises: generating a data structure including at least the monotonic counter value; generating a message authentication code (MAC) over the data structure using a first key; securely providing the data structure and the MAC to a module executed on the processor; the module verifying the MAC, comparing the monotonic counter value with a counter value stored during a previous suspend operation and, if the counter values match, then loading processor state required for the resume operation to complete. Another embodiment of a method comprises: generating a first key by a processor; securely sharing the first key with an off-processor component; and using the first key to generate a pairing ID usable to identify a pairing between the processor and the off-processor component.
摘要翻译：一种用于安全地挂起并恢复处理器状态的装置和方法。例如，方法的一个实施例包括：生成至少包括单调计数器值的数据结构; 使用第一密钥在数据结构上生成消息认证码（MAC）; 将数据结构和MAC安全地提供给在处理器上执行的模块; 所述模块验证所述MAC，将所述单调计数器值与在先前暂停操作期间存储的计数器值进行比较，并且如果所述计数器值匹配，则加载完成所述恢复操作所需的处理器状态。方法的另一实施例包括：由处理器生成第一密钥; 用脱离处理器组件安全地共享第一个密钥; 以及使用所述第一密钥来生成可用于识别所述处理器和所述关闭处理器组件之间的配对的配对ID。

4. 发明申请

US20220207149A1 DATA TAINTING TO MITIGATE SPECULATION VULNERABILITIES 有权
公开(公告)号：US20220207149A1
公开(公告)日：2022-06-30
申请号：US17134347
申请日：2020-12-26
申请人： Intel Corporation
发明人： Jason W. Brandt , Joseph Nuzman , Asit Mallick , Carlos Rozas
IPC分类号： G06F21/57 , G06F21/75 , G06F21/53
摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability detection hardware and execution hardware. The speculation vulnerability detection hardware is to detect vulnerability to a speculative execution attack and, in connection with a detection of vulnerability to a speculative execution attack, to provide an indication that data from a first operation is tainted. The execution hardware is to perform a second operation using the data if the second operation is to be performed non-speculatively and to prevent performance of the second operation if the second operation is to be performed speculatively and the data is tainted.

5. 发明申请

US20220206818A1 HARDENING EXECUTION HARDWARE AGAINST SPECULATION VULNERABILITIES 有权
公开(公告)号：US20220206818A1
公开(公告)日：2022-06-30
申请号：US17134334
申请日：2020-12-26
申请人： Intel Corporation
发明人： Alaa Alameldeen , Carlos Rozas , Fangfei Liu , Xiang Zou , Francis McKeen , Jason W. Brandt , Joseph Nuzman , Abhishek Basak , Scott Constable , Thomas Unterluggauer , Asit Mallick , Matthew Fernandez
IPC分类号： G06F9/38 , G06F9/30 , G06F21/57
摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a single instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the single instruction.

6. 发明授权

US11354482B2 Enabling stateless accelerator designs shared across mutually-distrustful tenants 有权
公开(公告)号：US11354482B2
公开(公告)日：2022-06-07
申请号：US17130407
申请日：2020-12-22
申请人： Intel Corporation
发明人： Alpa Trivedi , Carlos Rozas
IPC分类号： G06F30/398 , G06N3/04 , H04L9/00 , G06F9/30 , G06F15/177 , G06N20/00 , G06F11/07 , H04L9/08 , G06F9/50 , G06F15/78 , H04L9/40 , G06F30/331 , G06F9/38 , G06F119/12 , G06F21/76 , G06N3/08 , G06F21/85 , G06F111/04 , G06F30/31 , G06F21/30 , G06F21/53 , G06F21/57 , G06F21/73 , G06F21/74 , G06F21/71 , G06F21/44
摘要： An apparatus to facilitate enabling stateless accelerator designs shared across mutually-distrustful tenants is disclosed. The apparatus includes a fully-homomorphic encryption (FHE)-capable compute kernel. The FHE-capable compute kernel is to establish a secure session with a trusted environment executing on a host device communicably coupled to the apparatus; generate, as part of establishing the secure session, per-tenant FHE keys for each tenant utilizing the FHE-capable compute kernel, the per-tenant FHE keys utilized to encrypt tenant data provided to the FHE-capable compute kernel; process tenant data that is in an FHE-encrypted format encrypted with a per-tenant FHE key of the per-tenant FHE keys; and store the tenant data that is in the FHE-encrypted format encrypted with the per-tenant FHE key of the per-tenant FHE keys.

7. 发明申请

US20210111863A1 ENABLING STATELESS ACCELERATOR DESIGNS SHARED ACROSS MUTUALLY-DISTRUSTFUL TENANTS 有权
公开(公告)号：US20210111863A1
公开(公告)日：2021-04-15
申请号：US17130407
申请日：2020-12-22
申请人： Intel Corporation
发明人： Alpa Trivedi , Carlos Rozas
IPC分类号： H04L9/00 , H04L9/08 , G06F21/76 , G06N3/04
摘要： An apparatus to facilitate enabling stateless accelerator designs shared across mutually-distrustful tenants is disclosed. The apparatus includes a fully-homomorphic encryption (FHE)-capable compute kernel. The FHE-capable compute kernel is to establish a secure session with a trusted environment executing on a host device communicably coupled to the apparatus; generate, as part of establishing the secure session, per-tenant FHE keys for each tenant utilizing the FHE-capable compute kernel, the per-tenant FHE keys utilized to encrypt tenant data provided to the FHE-capable compute kernel; process tenant data that is in an FHE-encrypted format encrypted with a per-tenant FHE key of the per-tenant FHE keys; and store the tenant data that is in the FHE-encrypted format encrypted with the per-tenant FHE key of the per-tenant FHE keys.

8. 发明申请

US20200272474A1 RESTRICTED SPECULATIVE EXECUTION 审中-公开
公开(公告)号：US20200272474A1
公开(公告)日：2020-08-27
申请号：US16443593
申请日：2019-06-17
申请人： Intel Corporation
发明人： Ron Gabor , Alaa Alameldeen , Abhishek Basak , Fangfei Liu , Francis McKeen , Joseph Nuzman , Carlos Rozas , Igor Yanover , Xiang Zou
IPC分类号： G06F9/38 , G06F9/30 , G06F12/1027 , G06F21/57
摘要： Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

9. 发明申请

US20220207138A1 HARDENING STORE HARDWARE AGAINST SPECULATION VULNERABILITIES 有权
公开(公告)号：US20220207138A1
公开(公告)日：2022-06-30
申请号：US17134350
申请日：2020-12-26
申请人： Intel Corporation
发明人： Carlos Rozas , Fangfei Liu , Xiang Zou , Francis McKeen , Jason W. Brandt , Joseph Nuzman , Alaa Alameldeen , Abhishek Basak , Scott Constable , Thomas Unterluggauer , Asit Mallick , Matthew Fernandez
IPC分类号： G06F21/55 , G06F21/54 , G06F9/30 , G06F9/38
摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.

10. 发明申请

US20220200783A1 DEVICE, METHOD AND SYSTEM TO SUPPLEMENT A SKEWED CACHE WITH A VICTIM CACHE 有权
公开(公告)号：US20220200783A1
公开(公告)日：2022-06-23
申请号：US17127786
申请日：2020-12-18
申请人： Intel Corporation
发明人： Thomas Unterluggauer , Alaa Alameldeen , Scott Constable , Fangfei Liu , Francis McKeen , Carlos Rozas , Anna Trikalinou
IPC分类号： H04L9/00 , G06F21/72
摘要： Techniques and mechanisms for a victim cache to operate in conjunction with a skewed cache to help mitigate the risk of a side-channel attack. In an embodiment, a first line is evicted from a skewed cache, and moved to a victim cache, based on a message indicating that a second line is to be stored to the skewed cache. Subsequently, a request to access the first line results in a search of both the victim cache and sets of the skewed cache which have been mapped to an address corresponding to the first line. Based on the search, the first line is evicted from the victim cache, and reinserted in the skewed cache. In another embodiment, reinsertion of the first line in the skewed cache includes the first line and a third line being swapped between the skewed cache and the victim cache.

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