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1. 发明授权

US09015404B2 Persistent log operations for non-volatile memory 有权
标题翻译：用于非易失性存储器的持久日志操作
公开(公告)号：US09015404B2
公开(公告)日：2015-04-21
申请号：US13630548
申请日：2012-09-28
申请人： Intel Corporation
发明人： Ferad Zyulkyarov , Qiong Cai
IPC分类号： G06F9/06 , G06F9/30 , G06F12/02 , G06F11/14
CPC分类号： G06F9/467 , G06F11/141 , G06F11/1441 , G06F11/1471 , G06F11/1474 , G06F12/0246 , G06F2212/72
摘要： In an embodiment, a first delayed persistence operation to store information in a log contained in a non-volatile memory (NVM) may be performed. The information may include, for example, a current value of a variable contained in the NVM. A second delayed persistence operation to store information in the variable may be performed. A third delayed persistence operation to store information in the NVM that indicates the log is cleared may be performed. A flush operation may be performed, for example after the first, second, and third delayed persistence operations. The flush operation may commit information associated with at least one of the first, second, or third delayed persistence operations to the NVM.
摘要翻译：在一个实施例中，可以执行用于将信息存储在包含在非易失性存储器（NVM）中的日志中的第一延迟持续操作。该信息可以包括例如NVM中包含的变量的当前值。可以执行用于将信息存储在变量中的第二延迟持续操作。可以执行用于存储指示日志被清除的NVM中的信息的第三延迟持久性操作。可以执行刷新操作，例如在第一，第二和第三延迟持续操作之后。刷新操作可以将与第一，第二或第三延迟持久性操作中的至少一个相关联的信息提交给NVM。

2. 发明授权

US09286237B2 Memory imbalance prediction based cache management 有权
标题翻译：基于内存不平衡预测的缓存管理
公开(公告)号：US09286237B2
公开(公告)日：2016-03-15
申请号：US13793674
申请日：2013-03-11
申请人： Intel Corporation
发明人： Qiong Cai , Dyer Rolan , Blas Cuesta , Ferad Zyulkyarov , Serkan Ozdemir , Marios Nicolaides
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/12 , G06F12/122 , G06F2212/7211
摘要： Embodiments of methods, apparatuses, and storage media for memory imbalance prediction-based cache memory management are disclosed herein. In one instance, the apparatus may include a memory controller associated with a memory having a plurality of storage units. The memory controller may include logic configured to determine whether the memory enters into an imbalance state based at least in part on a difference in numbers of pending access requests to different storage units, and cause an adjustment of replacement management of a cache memory, based at least in part on a result of the determination. Other embodiments may be described and/or claimed.
摘要翻译：本文公开了用于基于存储器不平衡预测的高速缓冲存储器管理的方法，装置和存储介质的实施例。在一种情况下，该装置可以包括与具有多个存储单元的存储器相关联的存储器控制器。存储器控制器可以包括逻辑，其被配置为至少部分地基于对不同存储单元的未决访问请求的数量的差异来确定存储器是否进入不平衡状态，并且基于以下原因来调整高速缓冲存储器的替换管理至少部分取决于决定的结果。可以描述和/或要求保护其他实施例。

3. 发明申请

US20150227469A1 Method For Pinning Data In Large Cache In Multi-Level Memory System 有权
标题翻译：用于在多级存储器系统中的大型缓存中固定数据的方法
公开(公告)号：US20150227469A1
公开(公告)日：2015-08-13
申请号：US13976181
申请日：2013-03-15
申请人： Intel Corporation
发明人： Ferad Zyulkyarov , Nevin Hyuseinova , Qiong Cai , Blas Cuesta , Serkan Ozdemir , Marios Nicolaides
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/1045 , G06F12/0895 , G06F12/0897 , G06F12/126 , G06F2212/6022
摘要： A method to request memory from a far memory cache and implement, at an operating system (OS) level, a fully associative cache on the requested memory. The method includes pinning the working set of a program into the requested memory (pin buffer) so that it is not evicted due to cache conflicts and is served from the fast cache and not the slower next level memory. The requested memory extends the physical address space and is visible to and managed by the OS. The OS has the ability to make the requested memory visible to the user programs. The OS has the ability to manage the requested memory from the far memory cache as both a fully associative cache and a set associative cache.
摘要翻译：一种从远存储器高速缓存请求存储器并且在操作系统（OS）级别）实现所请求存储器上的完全关联高速缓存的方法。该方法包括将程序的工作集锁定到所请求的存储器（引脚缓冲器）中，使得它不会由于缓存冲突而被驱逐，并且从快速缓存而不是较慢的下一级存储器提供。所请求的内存扩展了物理地址空间，并且由操作系统可见和管理。操作系统能够使所请求的内存对用户程序可见。操作系统能够将远程存储器缓存中所请求的存储器作为完全关联缓存和集合关联高速缓存进行管理。

4. 发明授权

US09645942B2 Method for pinning data in large cache in multi-level memory system 有权
公开(公告)号：US09645942B2
公开(公告)日：2017-05-09
申请号：US13976181
申请日：2013-03-15
申请人： Intel Corporation
发明人： Ferad Zyulkyarov , Nevin Hyuseinova , Qiong Cai , Blas Cuesta , Serkan Ozdemir , Marios Nicolaides
IPC分类号： G06F12/00 , G06F12/1045 , G06F12/0897 , G06F12/126 , G06F12/0895
CPC分类号： G06F12/1045 , G06F12/0895 , G06F12/0897 , G06F12/126 , G06F2212/6022
摘要： A method to request memory from a far memory cache and implement, at an operating system (OS) level, a fully associative cache on the requested memory. The method includes pinning the working set of a program into the requested memory (pin buffer) so that it is not evicted due to cache conflicts and is served from the fast cache and not the slower next level memory. The requested memory extends the physical address space and is visible to and managed by the OS. The OS has the ability to make the requested memory visible to the user programs. The OS has the ability to manage the requested memory from the far memory cache as both a fully associative cache and a set associative cache.

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