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1. 发明授权

US11601121B2 Bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station and a mobile device 有权
公开(公告)号：US11601121B2
公开(公告)日：2023-03-07
申请号：US16912800
申请日：2020-06-26
申请人： Intel Corporation
发明人： Giacomo Cascio , Martin Clara , Christian Lindholm
IPC分类号： H03K17/041 , G11C27/02 , H03F3/45 , H03M1/12 , H04B1/40
摘要： The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor.

2. 发明申请

US20210409015A1 BOOTSTRAPPED SWITCH CIRCUIT, A TRACK-AND-HOLD CIRCUIT, AN ANALOG-TO-DIGITAL CONVERTER, A METHOD FOR OPERATING A TRACK-AND-HOLD CIRCUIT, A BASE STATION AND A MOBILE DEVICE 有权
公开(公告)号：US20210409015A1
公开(公告)日：2021-12-30
申请号：US16912800
申请日：2020-06-26
申请人： Intel Corporation
发明人： Giacomo Cascio , Martin Clara , Christian Lindholm
IPC分类号： H03K17/041 , H03M1/12 , G11C27/02 , H03F3/45 , H04B1/40
摘要： The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor.

3. 发明授权

US11489536B1 Input circuitry for an analog-to-digital converter, receiver, base station and method for operating an input circuitry for an analog-to-digital converter 有权
公开(公告)号：US11489536B1
公开(公告)日：2022-11-01
申请号：US17358093
申请日：2021-06-25
申请人： Intel Corporation
发明人： Martin Clara , Daniel Gruber , Giacomo Cascio , Albert Molina
IPC分类号： H03M1/10 , H04B1/12 , H04B1/48
摘要： Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.

4. 发明授权

US11082054B1 Apparatus and method for time-interleaved analog-to-digital conversion 有权
公开(公告)号：US11082054B1
公开(公告)日：2021-08-03
申请号：US16912812
申请日：2020-06-26
申请人： Intel Corporation
发明人： Giacomo Cascio , Christian Lindholm , Albert Molina , Martin Clara
IPC分类号： H03M1/12 , H03M1/06 , H03M1/36
摘要： The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank. The first ADC bank has associated therewith a first dummy sampler, wherein the ADC circuit is configured to activate the first dummy sampler before the start of the first time interval. The second ADC bank has associated therewith a second dummy sampler, wherein the ADC circuit is configured to activate the second dummy sampler before the start of the second time interval.

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