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1. 发明授权

US11531542B2 Addition instructions with independent carry chains 有权
公开(公告)号：US11531542B2
公开(公告)日：2022-12-20
申请号：US17393361
申请日：2021-08-03
申请人： Intel Corporation
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Matthew C. Merten , Tong Li , Bret L. Toll
IPC分类号： G06F9/30 , G06F9/38
摘要： A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

2. 发明授权

US10911222B2 Instructions processors, methods, and systems to process secure hash algorithms 有权
公开(公告)号：US10911222B2
公开(公告)日：2021-02-02
申请号：US16807021
申请日：2020-03-02
申请人： Intel Corporation
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
IPC分类号： H04L9/06 , G06F21/64 , G06F9/30 , G06F21/72 , G06F21/60
摘要： A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

3. 发明授权

US10725779B2 Method and apparatus to process SHA-2 secure hashing algorithm 有权
公开(公告)号：US10725779B2
公开(公告)日：2020-07-28
申请号：US16450319
申请日：2019-06-24
申请人： Intel Corporation
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30 , G06F21/60 , G06F12/0875 , G06F12/1027 , G09C1/00 , H04L9/32 , G06F9/38 , G06F12/0897 , G06F13/28 , G06F13/40 , G06F13/42 , G06F15/80 , H04L9/06
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

4. 发明授权

US10198248B2 Parallel processing of a single data buffer 有权
公开(公告)号：US10198248B2
公开(公告)日：2019-02-05
申请号：US13631761
申请日：2012-09-28
申请人： Intel Corporation
发明人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： G06F5/06 , G06F21/64 , H04L9/06 , H04L9/32
摘要： Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm.

5. 发明授权

US10089500B2 Secure modular exponentiation processors, methods, systems, and instructions 有权
公开(公告)号：US10089500B2
公开(公告)日：2018-10-02
申请号：US14866334
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： Vinodh Gopal , Gilbert M. Wolrich
IPC分类号： H04L29/00 , G06F21/72 , G06F9/30 , H04L9/08
摘要： A processor of an aspect includes a decode unit to decode a modular exponentiation with obfuscated input information instruction. The modular exponentiation with obfuscated input information instruction is to indicate a plurality of source operands that are to store input information for a modular exponentiation operation. At least some of the input information that is to be stored in the plurality of source operands is to be obfuscated. An execution unit is coupled with the decode unit. The execution unit, in response to the modular exponentiation with obfuscated input information instruction, is to store a modular exponentiation result in a destination storage location that is to be indicated by the modular exponentiation with obfuscated input information instruction. Other processors, methods, systems, and instructions are disclosed.

6. 发明申请

US20170111059A1 HETEROGENEOUS COMPRESSION ARCHITECTURE FOR OPTIMIZED COMPRESSION RATIO 有权
公开(公告)号：US20170111059A1
公开(公告)日：2017-04-20
申请号：US15393599
申请日：2016-12-29
申请人： Intel Corporation
发明人： James D. Guilford , Vinodh Gopal , Gilbert M. Wolrich , Daniel F. Cutter
IPC分类号： H03M7/40 , H03M7/30
CPC分类号： H03M7/40 , H03M7/30 , H03M7/3086
摘要： A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte position of the byte matches a second byte string starting from a second byte position, responsive to determining that the first byte string matches the second byte string, generate a token comprising a first symbol encoding a length of the first byte string and a second symbol encoding a byte distance between the first byte position and the second byte position, and responsive to determining that the first byte string does not match another byte string, generate the token comprising the first symbol comprising the byte and a second symbol encoding a determined value.

7. 发明申请

US20170083453A1 SUPPORTING DATA COMPRESSION USING MATCH SCORING 有权
公开(公告)号：US20170083453A1
公开(公告)日：2017-03-23
申请号：US15229478
申请日：2016-08-05
申请人： Intel Corporation
发明人： James D. Guilford , Vinodh Gopal , Gilbert M. Wolrich , Daniel F. Cutter
IPC分类号： G06F12/1018 , G06F12/1027 , G06F9/45
CPC分类号： G06F3/0638 , G06F3/0604 , G06F3/0608 , G06F3/0653 , G06F3/0673 , G06F8/52 , G06F12/1018 , G06F12/1027 , G06F2212/401 , G06F2212/68 , H03M7/3086 , H03M7/40
摘要： A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a first score based on: a first set of matching data related to a match between a first bit subsequence and a candidate bit subsequence within the input bit stream, and a first distance of the candidate bit subsequence from the first set of matching data. A second score is generated based on a second set of matching data related to a match between a second bit subsequence and the candidate bit subsequence, and a second distance of the candidate bit subsequence from the second set of matching data. A code to replace the first or second bit subsequence in an output bit stream is identified. Selection of the one of the bit subsequences to replace is based on a comparison of the scores.

8. 发明授权

US09537504B1 Heterogeneous compression architecture for optimized compression ratio 有权
标题翻译：用于优化压缩比的异构压缩架构
公开(公告)号：US09537504B1
公开(公告)日：2017-01-03
申请号：US14866115
申请日：2015-09-25
申请人： Intel Corporation
发明人： James D. Guilford , Vinodh Gopal , Gilbert M. Wolrich , Daniel F. Cutter
IPC分类号： H03M7/30 , H03M7/40
CPC分类号： H03M7/40 , H03M7/30 , H03M7/3086
摘要： A processing device includes a storage device to store data and a processor, operably coupled to the storage device, the processor to receive a token stream comprising a plurality of tokens generated based on a byte stream comprising a plurality of bytes, wherein each token in the token stream comprises at least one symbol associated with a respective byte in the byte stream, and wherein the at least one symbol represents one of the respective byte, a length of a first byte string starting from the respective byte, or a byte distance between the first byte string and a matching second byte string, generate a graph comprising a plurality of nodes and edges based on the token stream, wherein each token in the token stream is associated with a respective node connected by at least one edge to another node, and wherein the at least one edge is associated with a cost function to encode the at least one symbol stored in the each token, identify, based on the graph, a path between a first node associated with a beginning token of the token stream and an end node associated with a last token of the token stream, wherein the path comprises a subset of nodes and edges linking the subset of nodes, and perform variable-length encoding of a subset of tokens associated with the subset of nodes to generate an output data.
摘要翻译：处理设备包括存储数据的存储设备和可操作地耦合到存储设备的处理器，处理器接收包括基于包括多个字节的字节流生成的多个令牌的令牌流，其中，标记流包括与字节流中的相应字节相关联的至少一个符号，并且其中至少一个符号表示相应字节中的一个，从相应字节开始的第一字节串的长度，或第一字节串和匹配的第二字节串，基于令牌流生成包括多个节点和边的图形，其中令牌流中的每个令牌与由至少一个边缘连接到另一个节点的相应节点相关联，以及其中所述至少一个边缘与成本函数相关联，以对存储在每个令牌中的所述至少一个符号进行编码，基于所述图表来识别第一点之间的路径 e与令牌流的开始令牌和与令牌流的最后一个令牌相关联的结束节点相关联，其中该路径包括链接节点子集的节点和边缘的子集，并且执行子集的子集的可变长度编码与节点子集相关联的令牌以生成输出数据。

9. 发明授权

US09495165B2 Method and apparatus for performing a shift and exclusive or operation in a single instruction 有权
公开(公告)号：US09495165B2
公开(公告)日：2016-11-15
申请号：US14556931
申请日：2014-12-01
申请人： Intel Corporation
发明人： Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Wajdi K. Feghali , Gilbert M. Wolrich , Martin G. Dixon
IPC分类号： G06F7/00 , G06F7/38 , G06F1/02 , G06F17/50 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/3816 , G06F9/3893
摘要： Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

10. 发明申请

US20150256195A1 APPARATUS AND METHOD TO ACCELERATE COMPRESSION AND DECOMPRESSION OPERATIONS 有权
标题翻译：装置和方法来加速压缩和分解操作
公开(公告)号：US20150256195A1
公开(公告)日：2015-09-10
申请号：US14595129
申请日：2015-01-12
申请人： Intel Corporation
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich
IPC分类号： H03M7/30
CPC分类号： H03M7/3086 , G06F9/30145 , G06F9/30178
摘要： Methods and apparatuses relating to an instruction to decode encoded information of a compression scheme are described. In one embodiment, a processor includes a decode unit to decode an instruction, and an execution unit to execute the instruction, the execution unit including a state machine and content addressable memory (CAM) circuitry, the state machine to receive a pointer to a stream of encoded information of a compression scheme, fetch a section of the encoded information, and apply the section of the encoded information to the CAM circuitry to obtain decoded information.
摘要翻译：描述与解码压缩方案的编码信息的指令相关的方法和装置。在一个实施例中，处理器包括解码指令的解码单元和执行指令的执行单元，执行单元包括状态机和内容可寻址存储器（CAM）电路，状态机接收指向流的指针的压缩方案的编码信息，获取编码信息的一部分，并将编码信息的部分应用于CAM电路以获得解码信息。

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