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1. 发明授权

US09842015B2 Instruction and logic for machine checking communication 有权
公开(公告)号：US09842015B2
公开(公告)日：2017-12-12
申请号：US14040092
申请日：2013-09-27
申请人： INTEL CORPORATION
发明人： Ashok Raj , Mohan J. Kumar , Jose A. Vargas , William G. Auld , Cameron B. McNairy , Theodros Yigzaw , James B. Crossland , Anthony E. Luck
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0772 , G06F11/0712 , G06F11/0724 , G06F11/0784 , G06F11/0793
摘要： A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.

2. 发明授权

US09239801B2 Systems and methods for preventing unauthorized stack pivoting 有权
标题翻译：防止未经授权的堆叠枢转的系统和方法
公开(公告)号：US09239801B2
公开(公告)日：2016-01-19
申请号：US13910333
申请日：2013-06-05
申请人： Intel Corporation
发明人： Baiju V. Patel , Xiaoning Li , H P. Anvin , Asit K. Mallick , Gilbert Neiger , James B. Crossland , Toby Opferman , Atul A. Khare , Jason W. Brandt , James S. Coke , Brian L. Vajda
IPC分类号： G06F12/14 , G06F9/30 , G06F9/45
CPC分类号： G06F12/145 , G06F8/434 , G06F9/30105 , G06F9/30134 , G06F21/52
摘要： An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.
摘要翻译：示例处理系统可以包括：下堆叠绑定寄存器，被配置为存储第一存储器地址，第一存储器地址标识经由堆栈段可寻址的存储器的下限; 上堆叠绑定寄存器，其被配置为存储第二存储器地址，所述第二存储器地址通过所述堆栈段识别所述存储器可寻址的上限; 并且通过将经由所述堆栈段访问的存储器地址与所述第一存储器地址和所述第二存储器地址中的至少一个进行比较来配置用于检测未授权堆栈枢转的堆栈边界检查逻辑。

3. 发明申请

US20210357214A1 METHODS, APPARATUS, AND INSTRUCTIONS FOR USER-LEVEL THREAD SUSPENSION 有权
公开(公告)号：US20210357214A1
公开(公告)日：2021-11-18
申请号：US17334901
申请日：2021-05-31
申请人： Intel Corporation
发明人： Michael Mishaeli , Jason W. Brandt , Gilbert Neiger , Asit K. Mallick , Rajesh M. Sankaran , Raghunandan Makaram , Benjamin C. Chaffin , James B. Crossland , H. Peter Anvin
IPC分类号： G06F9/30 , G06F13/40 , G06F9/48 , G06F9/38
摘要： A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

4. 发明申请

US20170228233A1 METHODS, APPARATUS, AND INSTRUCTIONS FOR USER-LEVEL THREAD SUSPENSION 审中-公开
公开(公告)号：US20170228233A1
公开(公告)日：2017-08-10
申请号：US15019112
申请日：2016-02-09
申请人： INTEL CORPORATION
发明人： Michael Mishaeli , Jason W. Brandt , Gilbert Neiger , Asit K. Mallick , Rajesh M. Sankaran , Raghunandan Makaram , Benjamin C. Chaffin , James B. Crossland , H. Peter Anvin
IPC分类号： G06F9/30 , G06F13/40
CPC分类号： G06F9/3009 , G06F9/3004 , G06F9/30076 , G06F9/3851 , G06F9/52 , G06F13/4068
摘要： A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

5. 发明授权

US11074191B2 Linear to physical address translation with support for page attributes 有权
公开(公告)号：US11074191B2
公开(公告)日：2021-07-27
申请号：US15803244
申请日：2017-11-03
申请人： Intel Corporation
发明人： Ben-Zion Friedman , Jacob Doweck , Eliezer Weissmann , James B. Crossland , Ohad Falik
IPC分类号： G06F12/00 , G06F12/1009 , G06F12/1027 , G06F12/10 , G06F12/1036
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

6. 发明授权

US10001953B2 System for configuring partitions within non-volatile random access memory (NVRAM) as a replacement for traditional mass storage 有权
公开(公告)号：US10001953B2
公开(公告)日：2018-06-19
申请号：US15380266
申请日：2016-12-15
申请人： Intel Corporation
发明人： Leena K. Puthiyedath , Blaise Fanning , Toby Opferman , James B. Crossland
IPC分类号： G06F3/00 , G06F3/06 , G06F12/00 , G06F12/0804
CPC分类号： G06F3/0679 , G06F3/061 , G06F3/0631 , G06F3/0643 , G06F3/0644 , G06F12/00 , G06F12/0238 , G06F12/0638 , G06F12/08 , G06F12/0804 , G06F12/0866 , G06F2212/1004 , G06F2212/1056 , G06F2212/2024 , G06F2212/214 , G06F2212/251 , G06F2212/7201
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.

7. 发明申请

US20160378636A1 Software-Initiated Trace Integrated with Hardware Trace 审中-公开
标题翻译：软件启动跟踪与硬件跟踪集成
公开(公告)号：US20160378636A1
公开(公告)日：2016-12-29
申请号：US14751759
申请日：2015-06-26
申请人： Intel Corporation
发明人： Beeman C. Strong , Jason W. Brandt , Peter Lachner , Andreas Kleen , James B. Crossland , Toby Opferman
IPC分类号： G06F11/34 , G06F11/30
CPC分类号： G06F11/3466 , G06F11/3024 , G06F2201/865
摘要： In an embodiment, a processor includes a core that is to include fetch logic to fetch instructions that include first instructions and a second instruction. The core also includes execution logic to execute the instructions. The execution logic is to retrieve an operand value that is one of an immediate value, a register value, and a memory value stored in a memory location, responsive to execution of the second instruction. The core also includes logic to output a packet that includes a representation of the operand value responsive to execution of the second instruction. The core also includes processor trace (PT) logic to generate a processor trace that includes a plurality of PT packets, where each PT packet correspond to an outcome of execution of a respective first instruction. The processor trace logic is further to include the packet within the processor trace. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括一个核心，其核心是包括提取逻辑，以提取包括第一指令和第二指令的指令。核心还包括执行指令的执行逻辑。执行逻辑是响应于第二指令的执行，检索作为立即值，寄存器值和存储在存储单元中的存储器值之一的操作数值。核心还包括输出包括响应于执行第二指令的操作数值的表示的数据包的逻辑。核心还包括处理器跟踪（PT）逻辑以产生包括多个PT分组的处理器跟踪，其中每个PT分组对应于相应的第一指令的执行结果。处理器跟踪逻辑进一步将数据包包含在处理器跟踪内。描述和要求保护其他实施例。

8. 发明申请

US20160092227A1 Robust and High Performance Instructions for System Call 审中-公开
标题翻译：强大的高性能系统呼叫指令
公开(公告)号：US20160092227A1
公开(公告)日：2016-03-31
申请号：US14962883
申请日：2015-12-08
申请人： Intel Corporation
发明人： Baiju V. Patel , James B. Crossland , Atul A. Khare , Toby Opferman
IPC分类号： G06F9/30 , G06F9/54
CPC分类号： G06F9/30145 , G06F9/30054 , G06F9/52 , G06F9/54 , G06F2209/521
摘要： Robust system call and system return instructions are executed by a processor to transfer control between a requester and an operating system kernel. The processor includes execution circuitry and registers that store pointers to data structures in memory. The execution circuitry receives a system call instruction from a requester to transfer control from a first privilege level of the requester to a second privilege level of an operating system kernel. In response, the execution circuitry swaps the data structures that are pointed to by the registers between the requester and the operating system kernel in one atomic transition.
摘要翻译：强大的系统调用和系统返回指令由处理器执行，以在请求者和操作系统内核之间传输控制。处理器包括执行电路和寄存器，其存储指向存储器中的数据结构的指针。执行电路从请求者接收系统调用指令，以将控制从请求者的第一特权级别转移到操作系统内核的第二特权级别。作为响应，执行电路在一个原子转换中交换请求者和操作系统内核之间的寄存器所指向的数据结构。

9. 发明授权

US09158703B2 Linear to physical address translation with support for page attributes 有权
公开(公告)号：US09158703B2
公开(公告)日：2015-10-13
申请号：US14312669
申请日：2014-06-23
申请人： Intel Corporation
发明人： Ohad Falik , Ben-Zion Friedman , Jack Doweck , Eliezer Weissmann , James B. Crossland
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

10. 发明授权

US11023233B2 Methods, apparatus, and instructions for user level thread suspension 有权
公开(公告)号：US11023233B2
公开(公告)日：2021-06-01
申请号：US15019112
申请日：2016-02-09
申请人： INTEL CORPORATION
发明人： Michael Mishaeli , Jason W. Brandt , Gilbert Neiger , Asit K. Mallick , Rajesh M. Sankaran , Raghunandan Makaram , Benjamin C. Chaffin , James B. Crossland , H. Peter Anvin
IPC分类号： G06F9/30 , G06F13/40 , G06F9/48 , G06F9/38
摘要： A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

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