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1. 发明申请

US20220334948A1 METHODS AND APPARATUS TO IMPROVE PERFORMANCE DATA COLLECTION OF A HIGH PERFORMANCE COMPUTING APPLICATION 有权
公开(公告)号：US20220334948A1
公开(公告)日：2022-10-20
申请号：US17856148
申请日：2022-07-01
申请人： Intel Corporation
发明人： David Ozog , Md. Wasi-ur Rahman , James Dinan
IPC分类号： G06F11/34 , G06F11/30 , G06F13/40 , G06F11/36
摘要： Methods, apparatus, systems and articles of manufacture to improve performance data collection are disclosed. An example apparatus includes a performance data comparator of a source node to collect the performance data of an application of the source node from the host fabric interface at a polling frequency; an interface to transmit a write back instruction to the host fabric interface, the write back instruction to cause data to be written to a memory address location of memory of the source node to trigger a wake up mode; and a frequency selector to: start the polling frequency to a first polling frequency for a sleep mode; and increase the polling frequency to a second polling frequency in response to the data in the memory address location identifying the wake mode.

2. 发明授权

US10963183B2 Technologies for fine-grained completion tracking of memory buffer accesses 有权
公开(公告)号：US10963183B2
公开(公告)日：2021-03-30
申请号：US15463005
申请日：2017-03-20
申请人： Intel Corporation
发明人： James Dinan , Keith D. Underwood , Sayantan Sur , Charles A. Giefer , Mario Flajslik
IPC分类号： G06F3/06 , G06F13/16 , G06F13/28
摘要： Technologies for fine-grained completion tracking of memory buffer accesses include a compute device. The compute device is to establish multiple counter pairs for a memory buffer. Each counter pair includes a locally managed offset and a completion counter. The compute device is also to receive a request from a remote compute device to access the memory buffer, assign one of the counter pairs to the request, advance the locally managed offset of the assigned counter pair by the amount of data to be read or written, and advance the completion counter of the assigned counter pair as the data is read from or written to the memory buffer. Other embodiments are also described and claimed.

3. 发明申请

US20190188111A1 METHODS AND APPARATUS TO IMPROVE PERFORMANCE DATA COLLECTION OF A HIGH PERFORMANCE COMPUTING APPLICATION 审中-公开
公开(公告)号：US20190188111A1
公开(公告)日：2019-06-20
申请号：US16286095
申请日：2019-02-26
申请人： Intel Corporation
发明人： David Ozog , Md. Wasi-ur Rahman , James Dinan
IPC分类号： G06F11/34 , G06F11/36 , G06F13/40 , G06F11/30
CPC分类号： G06F11/3485 , G06F11/3041 , G06F11/3612 , G06F13/4027
摘要： Methods, apparatus, systems and articles of manufacture to improve performance data collection are disclosed. An example apparatus includes a performance data comparator of a source node to collect the performance data of an application of the source node from the host fabric interface at a polling frequency; an interface to transmit a write back instruction to the host fabric interface, the write back instruction to cause data to be written to a memory address location of memory of the source node to trigger a wake up mode; and a frequency selector to: start the polling frequency to a first polling frequency for a sleep mode; and increase the polling frequency to a second polling frequency in response to the data in the memory address location identifying the wake mode.

4. 发明授权

US10135711B2 Technologies for sideband performance tracing of network traffic 有权
公开(公告)号：US10135711B2
公开(公告)日：2018-11-20
申请号：US14979140
申请日：2015-12-22
申请人： Intel Corporation
发明人： Robert C. Zak , David Keppel , James Dinan
IPC分类号： H04L12/26 , H04L12/721
摘要： Technologies for tracing network performance include a network computing device configured to receive a network packet from a source endpoint node, process the received network packet, capture trace data corresponding to the network packet as it is processed by the network computing device, and transmit the received network packet to a target endpoint node. The network computing device is further configured to generate a trace data network packet that includes at least a portion of the captured trace data and transmit the trace data network packet to the destination endpoint node. The destination endpoint node is configured to monitor performance of the network by reconstructing a trace of the network packet based on the trace data of the trace data network packet. Other embodiments are described herein.

5. 发明申请

US20180267742A1 TECHNOLOGIES FOR FINE-GRAINED COMPLETION TRACKING OF MEMORY BUFFER ACCESSES 审中-公开
公开(公告)号：US20180267742A1
公开(公告)日：2018-09-20
申请号：US15463005
申请日：2017-03-20
申请人： Intel Corporation
发明人： James Dinan , Keith D. Underwood , Sayantan Sur , Charles A. Giefer , Mario Flajslik
IPC分类号： G06F3/06
CPC分类号： G06F3/0653 , G06F3/0616 , G06F3/0656 , G06F3/0673 , G06F13/1673 , G06F13/28
摘要： Technologies for fine-grained completion tracking of memory buffer accesses include a compute device. The compute device is to establish multiple counter pairs for a memory buffer. Each counter pair includes a locally managed offset and a completion counter. The compute device is also to receive a request from a remote compute device to access the memory buffer, assign one of the counter pairs to the request, advance the locally managed offset of the assigned counter pair by the amount of data to be read or written, and advance the completion counter of the assigned counter pair as the data is read from or written to the memory buffer. Other embodiments are also described and claimed.

6. 发明申请

US20170094010A1 Technologies for Automatic Processor Core Association Management and Communication Using Direct Data Placement in Private Caches 审中-公开
公开(公告)号：US20170094010A1
公开(公告)日：2017-03-30
申请号：US14864369
申请日：2015-09-24
申请人： Intel Corporation
发明人： James Dinan , Venkata Krishnan , Srinivas Sridharan , David A. Webb
IPC分类号： H04L29/08 , G06F9/455 , H04L12/24
CPC分类号： H04L67/2852 , G06F9/46
摘要： Technologies for communication with direct data placement include a number of computing nodes in communication over a network. Each computing node includes a many-core processor having an integrated host fabric interface (HFI) that maintains an association table (AT). In response to receiving a message from a remote device, the HFI determines whether the AT includes an entry associating one or more parameters of the message to a destination processor core. If so, the HFI causes a data transfer agent (DTA) of the destination core to receive the message data. The DTA may place the message data in a private cache of the destination core. Message parameters may include a destination process identifier or other network address and a virtual memory address range. The HFI may automatically update the AT based on communication operations generated by software executed by the processor cores. Other embodiments are described and claimed.

7. 发明申请

US20170085625A1 TECHNOLOGIES FOR HANDLING MESSAGE PASSING INTERFACE OPERATIONS 审中-公开
公开(公告)号：US20170085625A1
公开(公告)日：2017-03-23
申请号：US14858051
申请日：2015-09-18
申请人： Intel Corporation
发明人： James Dinan , Mario Flajslik , Keith D. Underwood
IPC分类号： H04L29/08 , H04L12/743 , H04L12/863
摘要： Technologies for handling message passing interface receive operations include a compute node to determine a plurality of parameters of a receive entry to be posted and determine whether the plurality of parameters includes a wildcard entry. The compute node generates a hash based on at least one parameter of the plurality of parameters in response to determining that the plurality of parameters does not include the wildcard entry and appends the receive entry to a list in a bin of a posted receive data structure, wherein the bin is determined based on the generated hash. The compute node further tracks the wildcard entry in the posted receive data structure in response to determining the plurality of parameters includes the wildcard entry and appends the receive entry to a wildcard list of the posted receive data structure in response to tracking the wildcard entry.

8. 发明申请

US20160314073A1 TECHNOLOGIES FOR SCALABLE REMOTELY ACCESSIBLE MEMORY SEGMENTS 审中-公开
标题翻译：可扩展的远程可用内存部分技术
公开(公告)号：US20160314073A1
公开(公告)日：2016-10-27
申请号：US14696719
申请日：2015-04-27
申请人： Intel Corporation
发明人： James Dinan , Mario Flajslik
IPC分类号： G06F12/10 , G06F15/173
CPC分类号： G06F15/17331 , G06F3/061 , G06F3/0659 , G06F3/067
摘要： Technologies for one-side remote memory access communication include multiple computing nodes in communication over a network. A receiver computing node receives a message from a sender node and extracts a segment identifier from the message. The receiver computing node determines, based on the segment identifier, a segment start address associated with a partitioned global address space (PGAS) segment of its local memory. The receiver computing node may index a segment table stored in the local memory or in a host fabric interface. The receiver computing node determines a local destination address within the PGAS segment based on the segment start address and an offset included in the message. The receiver computing node performs a remote memory access operation at the local destination address. The receiver computing node may perform those operations in hardware by the host fabric interface of the receiver computing node. Other embodiments are described and claimed.
摘要翻译：用于单侧远程存储器访问通信的技术包括通过网络进行通信的多个计算节点。接收机计算节点从发送方节点接收消息，并从消息中提取分段标识符。接收机计算节点基于段标识符确定与其本地存储器的分区全局地址空间（PGAS）段相关联的段起始地址。接收机计算节点可以索引存储在本地存储器或主机结构接口中的段表。接收机计算节点基于段起始地址和消息中包含的偏移来确定PGAS段内的本地目的地址。接收机计算节点在本地目的地地址执行远程存储器访问操作。接收机计算节点可以由接收机计算节点的主机结构接口在硬件中执行这些操作。描述和要求保护其他实施例。

9. 发明授权

US11194636B2 Technologies for generating triggered conditional events 有权
公开(公告)号：US11194636B2
公开(公告)日：2021-12-07
申请号：US15941509
申请日：2018-03-30
申请人： Intel Corporation
发明人： Mario Flajslik , Keith D. Underwood , Timo Schneider , James Dinan
IPC分类号： G06F9/54
摘要： Technologies for generating triggered conditional events operations include a host fabric interface (HFI) of a compute device configured to receive an operation execution command message associated with a triggered operation that has been fired, process the received operation execution command message to extract and store argument information from the received operation execution command, and increment an event counter associated with the fired triggered operation. The HFI is further configured to perform a triggered compare-and-generate event (TCAGE) operation as a function of the extracted argument information, determine whether to generate a triggering event, generate the triggering event as a function of the performed TCAGE operation, insert the generated triggered event into a triggered operation queue, and update the value of the event counter. Other embodiments are described herein.

10. 发明申请

US20210255910A1 ISOLATING COMMUNICATION STREAMS TO ACHIEVE HIGH PERFORMANCE MULTI-THREADED COMMUNICATION FOR GLOBAL ADDRESS SPACE PROGRAMS 有权
公开(公告)号：US20210255910A1
公开(公告)日：2021-08-19
申请号：US16880277
申请日：2020-05-21
申请人： Intel Corporation
发明人： Mario Flajslik , James Dinan
IPC分类号： G06F9/54 , G06F9/52
摘要： Systems, apparatuses and methods may provide for detecting an outbound communication and identifying a context of the outbound communication. Additionally, a completion status of the outbound communication may be tracked relative to the context. In one example, tracking the completion status includes incrementing a sent messages counter associated with the context in response to the outbound communication, detecting an acknowledgement of the outbound communication based on a network response to the outbound communication, incrementing a received acknowledgements counter associated with the context in response to the acknowledgement, comparing the sent messages counter to the received acknowledgements counter, and triggering a per-context memory ordering operation if the sent messages counter and the received acknowledgements counter have matching values.

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